Patents by Inventor Yi-Wang Zhan

Yi-Wang Zhan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200212042
    Abstract: A capacitor structure including a semiconductor substrate; a dielectric layer on the semiconductor substrate; a storage node pad in the dielectric layer; a lower electrode including a bottle-shaped bottom portion recessed into the dielectric layer and being in direct contact with the storage node pad; and a lattice layer supporting a topmost part of the lower electrode, wherein the lattice layer is not directly contacting the dielectric layer, but is directly contacting the topmost part of the lower electrode. The bottle-shaped bottom portion extends to a sidewall of the storage node pad. The bottle-shaped bottom portion has a width that is wider than other portion of the lower electrode.
    Type: Application
    Filed: March 9, 2020
    Publication date: July 2, 2020
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Wang Zhan, Chieh-Te Chen
  • Patent number: 10672648
    Abstract: A method of forming a semiconductor memory device includes following steps. First of all, a dielectric layer is formed on a semiconductor substrate, and a conductive pad is formed in the dielectric layer. Then, a stacked structure is formed on the dielectric layer, and the stacked structure includes a first layer, a second layer and a third layer stacked one over another on the conductive pad. Next, a patterned mask layer is formed on the stacked structure, and a portion of the stacked structure is removed, to form an opening in the stacked structure, with the opening having a tapered sidewall in the second layer and the first layer. After that, the tapered sidewall of the opening in the second layer is vertically etched, to form a contact opening in the stacked structure. Finally, the patterned mask layer is removed.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: June 2, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Wang Zhan
  • Patent number: 10658366
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a material layer having a contact pad therein; forming a dielectric layer on the material layer and the contact pad; forming a doped oxide layer on the dielectric layer; forming an oxide layer on the doped oxide layer; performing a first etching process to remove part of the oxide layer, part of the doped oxide layer, and part of the dielectric layer to form a first contact hole; performing a second etching process to remove part of the doped oxide layer to form a second contact hole; and forming a conductive layer in the second contact hole to form a contact plug.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: May 19, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chia-Liang Liao, Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen, Yi-Wang Zhan
  • Patent number: 10622362
    Abstract: A capacitor structure includes a semiconductor substrate, a dielectric layer disposed on the semiconductor substrate, a storage node pad disposed in the dielectric layer, and a cylindrical lower electrode including a bottom portion recessed into the dielectric layer and in contact with the storage node pad. The bottom extends to a sidewall of the storage node pad.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: April 14, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Wang Zhan, Chieh-Te Chen
  • Patent number: 10535610
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate having a scribe line region. A material layer is formed on the scribe line region and has a rectangular region defined therein. The rectangular region has a pair of first edges parallel with a widthwise direction of the scribe line region and a pair of second edges parallel with a lengthwise direction of the scribe line region. A pair of first alignment features is formed in the material layer along the first edges, and a pair of second alignment features is formed in the material layer along the second edges. The space between the pair of first alignment features is larger than a space between the pair of the second alignment features.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: January 14, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Wang Zhan, Chia-Liang Liao, Yu-Cheng Tung, Chien-Hao Chen, Chia-Hung Wang
  • Publication number: 20190304981
    Abstract: A capacitor structure includes a semiconductor substrate, a dielectric layer disposed on the semiconductor substrate, a storage node pad disposed in the dielectric layer, and a cylindrical lower electrode including a bottom portion recessed into the dielectric layer and in contact with the storage node pad. The bottom extends to a sidewall of the storage node pad.
    Type: Application
    Filed: June 18, 2019
    Publication date: October 3, 2019
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Wang Zhan, Chieh-Te Chen
  • Patent number: 10373957
    Abstract: A capacitor structure includes a semiconductor substrate, a dielectric layer disposed on the semiconductor substrate, a storage node pad disposed in the dielectric layer, and a cylindrical lower electrode including a bottom portion recessed into the dielectric layer and in contact with the storage node pad. The bottom extends to a sidewall of the storage node pad.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: August 6, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Wang Zhan, Chieh-Te Chen
  • Patent number: 10199258
    Abstract: A method of fabricating an isolation structure is provided. A first oxide layer and a first, second, and third hard mask layers are formed on a substrate. A patterned third hard mask layer is formed. Second oxide layers are formed on sidewalls of the patterned third hard mask layer and a fourth hard mask layer is formed between the second oxide layers. The second oxide layers and the second hard mask layer are removed using the patterned third hard mask layer and the fourth hard mask layer as a mask, to form a patterned second hard mask layer. The patterned third hard mask layer and the fourth hard mask layer are removed. A portion of the patterned second hard mask layer is removed to form trench patterns. A patterned first hard mask layer and first oxide layer, and trenches located in the substrate are defined. An isolation material is formed.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: February 5, 2019
    Assignees: United Microelectronics Corp., Fujian Jianhua Integrated Circuit Co., Ltd.
    Inventors: Chieh-Te Chen, Hsien-Shih Chu, Ming-Feng Kuo, Fu-Che Lee, Chien-Ting Ho, Chiung-Lin Hsu, Feng-Yi Chang, Yi-Wang Zhan, Li-Chiang Chen, Chien-Cheng Tsai, Chin-Hsin Chiu
  • Publication number: 20190035743
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate having a scribe line region. A material layer is formed on the scribe line region and has a rectangular region defined therein. The rectangular region has a pair of first edges parallel with a widthwise direction of the scribe line region and a pair of second edges parallel with a lengthwise direction of the scribe line region. A pair of first alignment features is formed in the material layer along the first edges, and a pair of second alignment features is formed in the material layer along the second edges. The space between the pair of first alignment features is larger than a space between the pair of the second alignment features.
    Type: Application
    Filed: June 7, 2018
    Publication date: January 31, 2019
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Wang Zhan, Chia-Liang Liao, Yu-Cheng Tung, Chien-Hao Chen, Chia-Hung Wang
  • Patent number: 10192777
    Abstract: A method of fabricating an STI trench includes providing a substrate. Later, a first mask is formed to cover the substrate. The first mask includes numerous sub-masks. A first trench is disposed between each sub-mask. Subsequently, a protective layer is formed to fill up the first trench. Then, a second mask is formed to cover the first mask. The second mask includes an opening. The sub-mask directly disposed under the opening is defined as a joint STI pattern. After that, the joint STI pattern is removed to transform the first mask into a third mask. Later, the second mask is removed followed by removing the protective layer. Finally, part of the substrate is removed by taking the third mask as a mask to form numerous STI trenches.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: January 29, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Hsien-Shih Chu, Ming-Feng Kuo, Yi-Wang Zhan, Li-Chiang Chen, Fu-Che Lee, Feng-Yi Chang
  • Patent number: 10170310
    Abstract: A method of forming a patterned structure is provided in the present invention. A hard mask layer is formed on a material layer before a first etching process and a second etching process for forming a first opening and a second opening partially overlapping with each other in the hard mask layer. The hard mask layer having the first opening and the second opening is then used in a third etching process performed to the material layer. A fourth etching process is performed to the hard mask layer and a dielectric layer disposed under the material layer after the third etching process. The material of the hard mask layer is identical to the material of the dielectric layer, and the fourth etching process may be used to remove the hard mask layer and form a trench in the dielectric layer accordingly.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: January 1, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chieh-Te Chen, Feng-Yi Chang, Fu-Che Lee, Yi-Wang Zhan
  • Publication number: 20180315759
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a material layer having a contact pad therein; forming a dielectric layer on the material layer and the contact pad; forming a doped oxide layer on the dielectric layer; forming an oxide layer on the doped oxide layer; performing a first etching process to remove part of the oxide layer, part of the doped oxide layer, and part of the dielectric layer to form a first contact hole; performing a second etching process to remove part of the doped oxide layer to form a second contact hole; and forming a conductive layer in the second contact hole to form a contact plug.
    Type: Application
    Filed: March 14, 2018
    Publication date: November 1, 2018
    Inventors: Chia-Liang Liao, Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen, Yi-Wang Zhan
  • Publication number: 20180286867
    Abstract: A method of forming a semiconductor memory device includes following steps. First of all, a dielectric layer is formed on a semiconductor substrate, and a conductive pad is formed in the dielectric layer. Then, a stacked structure is formed on the dielectric layer, and the stacked structure includes a first layer, a second layer and a third layer stacked one over another on the conductive pad. Next, a patterned mask layer is formed on the stacked structure, and a portion of the stacked structure is removed, to form an opening in the stacked structure, with the opening having a taped sidewall in the second layer and the first layer. After that, the taped sidewall of the opening in the second layer is vertically etched, to form a contact opening in the stacked structure. Finally, the patterned mask layer is removed.
    Type: Application
    Filed: March 27, 2018
    Publication date: October 4, 2018
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Wang Zhan
  • Publication number: 20180190538
    Abstract: A method of fabricating an STI trench includes providing a substrate. Later, a first mask is formed to cover the substrate. The first mask includes numerous sub-masks. A first trench is disposed between each sub-mask. Subsequently, a protective layer is formed to fill up the first trench. Then, a second mask is formed to cover the first mask. The second mask includes an opening. The sub-mask directly disposed under the opening is defined as a joint STI pattern. After that, the joint STI pattern is removed to transform the first mask into a third mask. Later, the second mask is removed followed by removing the protective layer. Finally, part of the substrate is removed by taking the third mask as a mask to form numerous STI trenches.
    Type: Application
    Filed: December 27, 2017
    Publication date: July 5, 2018
    Inventors: Hsien-Shih Chu, Ming-Feng Kuo, Yi-Wang Zhan, Li-Chiang Chen, Fu-Che Lee, Feng-Yi Chang
  • Publication number: 20180190657
    Abstract: A capacitor structure includes a semiconductor substrate, a dielectric layer disposed on the semiconductor substrate, a storage node pad disposed in the dielectric layer, and a cylindrical lower electrode including a bottom portion recessed into the dielectric layer and in contact with the storage node pad. The bottom extends to a sidewall of the storage node pad.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 5, 2018
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Wang Zhan, Chieh-Te Chen
  • Publication number: 20180108563
    Abstract: A method of fabricating an isolation structure is provided. A first oxide layer and a first, second, and third hard mask layers are formed on a substrate. A patterned third hard mask layer is formed. Second oxide layers are formed on sidewalls of the patterned third hard mask layer and a fourth hard mask layer is formed between the second oxide layers. The second oxide layers and the second hard mask layer are removed using the patterned third hard mask layer and the fourth hard mask layer as a mask, to form a patterned second hard mask layer. The patterned third hard mask layer and the fourth hard mask layer are removed. A portion of the patterned second hard mask layer is removed to form trench patterns. A patterned first hard mask layer and first oxide layer, and trenches located in the substrate are defined. An isolation material is formed.
    Type: Application
    Filed: December 20, 2016
    Publication date: April 19, 2018
    Applicants: United Microelectronics Corp., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chieh-Te Chen, Hsien-Shih Chu, Ming-Feng Kuo, Fu-Che Lee, Chien-Ting Ho, Chiung-Lin Hsu, Feng-Yi Chang, Yi-Wang Zhan, Li-Chiang Chen, Chien-Cheng Tsai, Chin-Hsin Chiu