Patents by Inventor Yi-Wei Chiu

Yi-Wei Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210013590
    Abstract: A mobile device includes a system circuit board, a metal frame, a first feeding element, an RF (Radio Frequency) module, and one or more other antenna elements. The system circuit board includes a system ground plane. The metal frame includes a first portion and a second portion. The metal frame has a first cut point positioned between the first portion and the second portion. The first feeding element is directly or indirectly electrically connected to the first portion. A first antenna structure is formed by the first feeding element and the first portion. The second portion is excited by the first antenna structure using a coupling mechanism. The RF module is electrically coupled to the first feeding element. The metal frame further has a second cut point for separating the other antenna elements from the first antenna structure.
    Type: Application
    Filed: September 30, 2020
    Publication date: January 14, 2021
    Applicant: HTC Corporation
    Inventors: Tiao-Hsing TSAI, Chien-Pin CHIU, Hsiao-Wei WU, Li-Yuan FANG, Shen-Fu TZENG, Yi-Hsiang KUNG
  • Patent number: 10879588
    Abstract: A mobile device includes a system circuit board, a metal frame, a first feeding element, a second feeding element, and an RF (Radio Frequency) module. The system circuit board includes a system ground plane. The metal frame includes a first portion and a second portion. The metal frame has a first cut point positioned between the first portion and the second portion. The first feeding element is directly or indirectly electrically connected to the first portion. A first antenna structure is formed by the first feeding element and the first portion. The second feeding element is directly or indirectly electrically connected to the second portion. A second antenna structure is formed by the second feeding element and the second portion. The RF module is electrically coupled to the first feeding element and the second feeding element, so as to excite the first antenna structure and second antenna structure.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: December 29, 2020
    Assignee: HTC CORPORATION
    Inventors: Tiao-Hsing Tsai, Chien-Pin Chiu, Hsiao-Wei Wu, Li-Yuan Fang, Shen-Fu Tzeng, Yi-Hsiang Kung
  • Patent number: 10879051
    Abstract: A plasma processing apparatus is provided. The apparatus includes a lower sheltering module. The apparatus further includes an upper sheltering module arranged adjacent to the lower sheltering module. The apparatus includes an upper plate and an upper PEZ ring positioned around the upper plate. The apparatus also includes a shadowing unit that includes a number of engaging parts in the form of arcs detachably positioned on the upper PEZ ring. In addition, the apparatus includes a plasma generation module for generating plasma in the peripheral region of the lower sheltering module and the upper sheltering module.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsing Wu, Hung-Jui Chang, Chih-Ching Cheng, Yi-Wei Chiu, Kun-Cheng Chen
  • Patent number: 10878928
    Abstract: Various embodiments of the present application are directed towards a one-time-programmable (OTP) implementation using magnetic junctions. In some embodiments, an array comprises multiple magnetic junctions in multiple columns and multiple rows, and the magnetic junctions comprise a first magnetic junction and a second magnetic junction. The first and second magnetic junctions comprise individual top ferromagnetic elements and individual bottom ferromagnetic elements, and further comprise individual barrier elements between the top and bottom ferromagnetic elements. A first barrier element of the first magnetic junction electrically separates first top and bottom ferromagnetic elements of the first magnetic junction. A second barrier element of the second magnetic junction has undergone breakdown, such that it has defects defining a leakage path between second top and bottom ferromagnetic elements of the second magnetic junction.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Tien-Wei Chiang, Wen-Chun You, Yi-Chieh Chiu, Yu-Lin Chen, Jian-Cheng Huang, Chang-Hung Chen
  • Patent number: 10879109
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a recess in a layer. The recess has two opposite first inner walls and two opposite second inner walls, the first inner walls are spaced apart by a first distance, the second inner walls are spaced apart by a second distance, and the first distance is less than the second distance. The method includes depositing a first covering layer in the recess. The first covering layer covering the first inner walls is thinner than the first covering layer covering the second inner walls. The method includes removing the first covering layer over the first inner walls and a bottom surface of the recess.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Xi-Zong Chen, Chih-Hsuan Lin, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu
  • Publication number: 20200402859
    Abstract: An apparatus includes a first source and a common drain and on opposite sides of a first gate surrounded by a first gate spacer, a second source and the common drain on opposite sides of a second gate surrounded by a second gate spacer, a first protection layer formed along a sidewall of the first gate spacer, wherein a top surface of the first protection layer has a first slope, a second protection layer formed along a sidewall of the second gate spacer, wherein a top surface of the second protection layer has a second slope, a lower drain contact between the first gate and the second gate and an upper drain contact over the lower drain contact and between the first gate and the second gate, wherein at least a portion of the upper drain contact is in contact with the first slope and the second slope.
    Type: Application
    Filed: September 3, 2020
    Publication date: December 24, 2020
    Inventors: Wan Hsuan Hsu, I-Hsiu Wang, Yean-Zhaw Chen, Cheng-Wei Chang, Yu Shih Wang, Hsin-Yan Lu, Yi-Wei Chiu
  • Publication number: 20200403077
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Inventors: Chun-Chieh Chiu, Pin-Hong Chen, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chien Liu, Tzu-Chieh Chen, Chih-Chieh Tsai, Kai-Jiun Chang, Yi-An Huang, Chia-Chen Wu, Tzu-Hao Liu
  • Patent number: 10861800
    Abstract: An integrated circuit structure includes a semiconductor substrate having a plurality of semiconductor strips, a first recess being formed by two adjacent semiconductor strips among the plurality of semiconductor strips, a second recess being formed within the first recess, and an isolation region being provided in the first recess and the second recess. The second recess has a lower depth than the first recess.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Chun Kuan, Chih-Teng Liao, Yi-Wei Chiu, Tzu-Chan Weng
  • Patent number: 10854603
    Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Chih Hsueh, Chih-Chang Hung, Tsung Fan Yin, Yi-Wei Chiu
  • Patent number: 10847349
    Abstract: A semiconductor manufacturing method and semiconductor manufacturing tool for performing the same are disclosed. The semiconductor manufacturing tool includes a plasma chamber, a mounting platform disposed within the plasma chamber, a focus ring disposed within the plasma chamber, and at least one actuator mechanically coupled to the focus ring and configured to move the focus ring vertically. The actuator is configured to move the focus ring vertically when a plasma is present in the plasma chamber.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chi Lin, Yi-Wei Chiu, Hung Jui Chang, Chin-Hsing Lin
  • Publication number: 20200365767
    Abstract: A light-emitting diode structure includes a substrate, a light-generating structure disposed over the substrate, a first electrode adjacent to a first side of the light-generating structure, a second electrode adjacent to a second side of the light-generating structure opposite to the first side, and a tungsten-doped oxide layer disposed in an electrical conduction path between the light-generating structure and one of the first electrode and the second electrode.
    Type: Application
    Filed: October 29, 2019
    Publication date: November 19, 2020
    Inventors: MUNEHISA YANAGISAWA, CHUN-NENG HUANG, CHI-HUNG FENG, HSING-HSUAN LO, TING-WEI CHANG, YI-HSIANG CHIU
  • Publication number: 20200357913
    Abstract: A finFET device and a method of forming are provided. The device includes a transistor comprising a gate electrode and a first source/drain region next to the gate electrode, the gate electrode being disposed over a first substrate. The device also includes a first dielectric layer extending along the first source/drain region, and a second dielectric layer overlying the first dielectric layer. The device also includes a contact disposed in the first dielectric layer and in the second dielectric layer, the contact contacting the gate electrode and the first source/drain region. A first portion of the first dielectric layer extends between the contact and the gate electrode. The contact extends along a sidewall of the first portion of the first dielectric layer and a first surface of the first portion of the first dielectric layer, the first surface of the first portion being farthest from the first substrate.
    Type: Application
    Filed: July 23, 2020
    Publication date: November 12, 2020
    Inventors: Xi-Zong Chen, Te-Chih Hsiung, Cha-Hsin Chao, Yi-Wei Chiu
  • Publication number: 20200357688
    Abstract: A device includes a substrate, a first dielectric layer over the substrate, a first conductive feature in the first dielectric layer, and an etch stop layer over the first dielectric layer. The etch stop layer includes metal-doped aluminum nitride. The device further includes a second dielectric layer over the etch stop layer, and a second conductive feature in the second dielectric layer. The second conductive feature extends into the etch stop layer and contacts the first conductive feature.
    Type: Application
    Filed: July 29, 2020
    Publication date: November 12, 2020
    Inventors: Chia-Ching Tsai, Yi-Wei Chiu, Li-Te Hsu
  • Patent number: 10833914
    Abstract: Certain aspects direct to systems and methods for device or vendor independent network switch management on a management controller. The management controller is communicatively connected to a network switch through a Simple Network Management Protocol (SNMP) interface. The management controller receives parsed information of a management information base (MIB) file corresponding to the network switch, and establishes a communication between the management controller and the network switch through the SNMP interface based on the parsed information of the MIB file, in which the management controller functions as a client and the network switch functions as a server of the communication. Then the management controller receives an input to manage and configure the network switch, and manages and configures the network switch via the communication through the SNMP interface based on the input and the parsed information of the MIB file.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: November 10, 2020
    Assignee: MAERICAN MEGATRENDS INTERNATIONAL, LLC
    Inventors: Anurag Bhatia, Yi-Wei Chiu, George Hsin, Kiran Kumar Ballapalli, Ajay Kumar Gupta
  • Patent number: 10825739
    Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor strip protruding above a substrate, forming isolation regions on opposing sides of the semiconductor strip, recessing the isolation regions in a first chamber using a first etching process, and increasing a planarity of the isolation regions in the first chamber using a second etching process.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Chun Kuan, Yi-Wei Chiu, Tzu-Chan Weng, Meng-Je Chuang
  • Patent number: 10825727
    Abstract: A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric, and forming a source/drain region extending into the semiconductor region. The method further includes forming a source/drain contact plug over and electrically coupling to the source/drain region, and forming a gate contact plug over and in contact with the gate electrode. At least one of the forming the gate electrode, the forming the source/drain contact plug, and the forming the gate contact plug includes forming a metal nitride barrier layer, and depositing a metal-containing layer over and in contact with the metal nitride barrier layer. The metal-containing layer includes at least one of a cobalt layer and a metal silicide layer.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ching Tsai, Yi-Wei Chiu, Li-Te Hsu
  • Patent number: 10812505
    Abstract: A computer system includes an openflow switch, configured to receive a plurality of packets; a network controller, coupled to the openflow switch and configured to determine a route of each of the plurality of packets; and a detecting and defending system, configured to perform transformation of information formats of the plurality of packets, retrieve and label the plurality of packets to determine whether the plurality of packets are abnormal or not and generate a defending determination.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: October 20, 2020
    Assignee: National Chung-Shan Institute of Science and Technology
    Inventors: Li-Der Chou, Chia-Wei Tseng, Chia-Kuan Yen, Wei-Hsiang Tsai, Tsung-Fu Ou, Yi-Hsuan Chiu, Wei-Yu Chen, Meng-Sheng Lai
  • Publication number: 20200328113
    Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.
    Type: Application
    Filed: June 25, 2020
    Publication date: October 15, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Allen Ke, Yi-Wei CHIU, Hung Jui CHANG, Yu-Wei KUO
  • Patent number: 10804365
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: October 13, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chun-Chieh Chiu, Pin-Hong Chen, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chien Liu, Tzu-Chieh Chen, Chih-Chieh Tsai, Kai-Jiun Chang, Yi-An Huang, Chia-Chen Wu, Tzu-Hao Liu
  • Patent number: 10804149
    Abstract: A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tsang Hsieh, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu, Ying Ting Hsia