Patents by Inventor Yi-Wei Chiu

Yi-Wei Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250246528
    Abstract: A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70° and about 80° and a depth ratio of between about 65% and about 70%.
    Type: Application
    Filed: April 17, 2025
    Publication date: July 31, 2025
    Inventors: Chia-Ching Tsai, Yi-Wei Chiu, Hung Jui Chang, Li-Te Hsu
  • Publication number: 20250226263
    Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a second ILD layer over the first ILD layer, forming a source/drain contact structure within the first ILD layer and the second ILD layer, and selectively removing a portion of the source/drain contact structure to form a concave top surface of the source/drain contact structure.
    Type: Application
    Filed: January 17, 2025
    Publication date: July 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Yu HSIEH, Ying-Ting HSIA, Jeng Chang HER, Cha-Hsin CHAO, Yi-Wei CHIU, Li-Te HSU
  • Patent number: 12354913
    Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a second ILD layer over the first ILD layer, forming a source/drain contact structure within the first ILD layer and the second ILD layer, and selectively removing a portion of the source/drain contact structure to form a concave top surface of the source/drain contact structure.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: July 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Yu Hsieh, Ying Ting Hsia, Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Li-Te Hsu
  • Patent number: 12347729
    Abstract: A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric, and forming a source/drain region extending into the semiconductor region. The method further includes forming a source/drain contact plug over and electrically coupling to the source/drain region, and forming a gate contact plug over and in contact with the gate electrode. At least one of the forming the gate electrode, the forming the source/drain contact plug, and the forming the gate contact plug includes forming a metal nitride barrier layer, and depositing a metal-containing layer over and in contact with the metal nitride barrier layer. The metal-containing layer includes at least one of a cobalt layer and a metal silicide layer.
    Type: Grant
    Filed: September 27, 2023
    Date of Patent: July 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ching Tsai, Yi-Wei Chiu, Li-Te Hsu
  • Patent number: 12322648
    Abstract: The present disclosure describes a method for forming a silicon-based, carbon-rich, low-k ILD layer with a carbon concentration between about 15 atomic % and about 20 atomic %. For example, the method includes depositing a dielectric layer, over a substrate, with a dielectric material having a dielectric constant below 3.9 and a carbon atomic concentration between about 15% and about 20%; exposing the dielectric layer to a thermal process configured to outgas the dielectric material; etching the dielectric layer to form openings; and filling the openings with a conductive material to form conductive structures.
    Type: Grant
    Filed: July 12, 2023
    Date of Patent: June 3, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Joung-Wei Liou, Yi-Wei Chiu, Bo-Jhih Shen
  • Publication number: 20250174493
    Abstract: The present disclosure describes a method for forming a silicon-based, carbon-rich, low-k ILD layer with a carbon concentration between about 15 atomic % and about 20 atomic %. For example, the method includes depositing a dielectric layer, over a substrate, with a dielectric material having a dielectric constant below 3.9 and a carbon atomic concentration between about 15% and about 20%.; exposing the dielectric layer to a thermal process configured to outgas the dielectric material; etching the dielectric layer to form openings; and filling the openings with a conductive material to form conductive structures.
    Type: Application
    Filed: January 17, 2025
    Publication date: May 29, 2025
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Joung-Wei LIOU, Yi-Wei Chiu, Bo-Jhih Shen
  • Patent number: 12300741
    Abstract: A method includes forming a semiconductor fin extending a first height above a substrate, forming a dummy dielectric material over the semiconductor fin and over the substrate, forming a dummy gate material over the dummy dielectric material, the dummy gate material extending a second height above the substrate, etching the dummy gate material using multiple etching processes to form a dummy gate stack, wherein each etching process of the multiple etching processes is a different etching process, wherein the dummy gate stack has a first width at the first height, and wherein the dummy gate stack has a second width at the second height that is different from the first width.
    Type: Grant
    Filed: March 6, 2023
    Date of Patent: May 13, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Teng Liao, Chia-Cheng Tai, Tzu-Chan Weng, Yi-Wei Chiu, Chih Hsuan Cheng
  • Patent number: 12300593
    Abstract: A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70° and about 80° and a depth ratio of between about 65% and about 70%.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: May 13, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ching Tsai, Yi-Wei Chiu, Hung Jui Chang, Li-Te Hsu
  • Patent number: 12266567
    Abstract: Implementations of the present disclosure provide methods for preventing contact damage or oxidation after via/trench opening formation. In one example, the method includes forming an opening in a structure on the substrate to expose a portion of a surface of an electrically conductive feature, and bombarding a surface of a mask layer of the structure using energy species formed from a plasma to release reactive species from the mask layer, wherein the released reactive species form a barrier layer on the exposed surface of the electrically conductive feature.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Jhih Shen, Yi-Wei Chiu, Hung Jui Chang
  • Patent number: 12154608
    Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bo-Jhih Shen, Kuang-I Liu, Joung-Wei Liou, Jinn-Kwei Liang, Yi-Wei Chiu, Chin-Hsing Lin, Li-Te Hsu, Han-Ting Tsai, Cheng-Yi Wu, Shih-Ho Lin
  • Publication number: 20240371870
    Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Inventors: Jen-Chih Hsueh, Chih-Chang Hung, Tsung Fan Yin, Yi-Wei Chiu
  • Publication number: 20240363336
    Abstract: Methods to form low-k dielectric materials for use as intermetal dielectrics in multilevel interconnect systems, along with their chemical and physical properties, are provided. The deposition techniques described include PECVD, PEALD, and ALD processes where the precursors such as TEOS and MDEOS may provide the requisite O-atoms and O2 gas may not be used as one of the reactants. The deposition techniques described further include PECVD, PEALD, and ALD processes where O2 gas may be used and, along with the O2 gas, precursors containing embedded Si—O—Si bonds, such as (CH3O)3—Si—O—Si—(CH3O)3) and (CH3)3—Si—O—Si—(CH3)3 may be used.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Inventors: Joung-Wei Liou, Yu Lun Ke, Yi-Wei Chiu
  • Publication number: 20240363409
    Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chen-Yuan Kao, Yi-Wei Chiu, Liang-Yueh Ou Yang, Yueh-Ching Pai
  • Patent number: 12094877
    Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jen-Chih Hsueh, Chih-Chang Hung, Tsung Fan Yin, Yi-Wei Chiu
  • Patent number: 12080547
    Abstract: Methods to form low-k dielectric materials for use as intermetal dielectrics in multilevel interconnect systems, along with their chemical and physical properties, are provided. The deposition techniques described include PECVD, PEALD, and ALD processes where the precursors such as TEOS and MDEOS may provide the requisite O-atoms and O2 gas may not be used as one of the reactants. The deposition techniques described further include PECVD, PEALD, and ALD processes where O2 gas may be used and, along with the O2 gas, precursors containing embedded Si—O—Si bonds, such as (CH3O)3—Si—O—Si—(CH3O)3) and (CH3)3—Si—O—Si—(CH3)3 may be used.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: September 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Joung-Wei Liou, Yu Lun Ke, Yi-Wei Chiu
  • Patent number: 12074032
    Abstract: A chamber door, such as an etch chamber door may be heated during etch processing to, e.g., prevent etching by-products from adhering to the etch chamber door. Such heating of the etch chamber door, however, can impact the processing parameters and result in non-uniform processing, such as non-uniform etching characteristics across a semiconductor wafer, for instance. An insulator, such as an insulating film covering surfaces of the heated door, can reduce or eliminate transmission of heat from the door to a work piece such as a semiconductor wafer and this reduce or eliminate the non-uniformity of the process results.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: August 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Je Chuang, Wan-Chun Kuan, Yi-Wei Chiu, Tzu-Chan Weng
  • Patent number: 12068197
    Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: August 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Sheng Wang, Chi-Cheng Hung, Chen-Yuan Kao, Yi-Wei Chiu, Liang-Yueh Ou Yang, Yueh-Ching Pai
  • Publication number: 20240274467
    Abstract: A device includes a substrate, a first dielectric layer over the substrate, a first conductive feature in the first dielectric layer, and an etch stop layer over the first dielectric layer. The etch stop layer includes metal-doped aluminum nitride. The device further includes a second dielectric layer over the etch stop layer, and a second conductive feature in the second dielectric layer. The second conductive feature extends into the etch stop layer and contacts the first conductive feature.
    Type: Application
    Filed: April 26, 2024
    Publication date: August 15, 2024
    Inventors: Chia-Ching Tsai, Yi-Wei Chiu, Li-Te Hsu
  • Patent number: 12015070
    Abstract: A method of forming a gate structure includes forming an opening through an insulating layer and forming a first work function metal layer in the opening. The method also includes recessing the first work function metal layer into the opening to form a recessed first work function metal layer, and forming a second work function metal layer in the opening and over the first work function metal layer. The second work function metal layer lines and overhangs the recessed first work function metal layer.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: June 18, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Chun Chen, Tsung Fan Yin, Li-Te Hsu, Ying Ting Hsia, Yi-Wei Chiu
  • Patent number: 11996325
    Abstract: A device includes a substrate, a first dielectric layer over the substrate, a first conductive feature in the first dielectric layer, and an etch stop layer over the first dielectric layer. The etch stop layer includes metal-doped aluminum nitride. The device further includes a second dielectric layer over the etch stop layer, and a second conductive feature in the second dielectric layer. The second conductive feature extends into the etch stop layer and contacts the first conductive feature.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ching Tsai, Yi-Wei Chiu, Li-Te Hsu