Abstract: A semiconductor structure includes a nucleation layer disposed on a substrate, an epitaxial growth layer disposed above the nucleation layer, and a superlattice structure disposed between the nucleation layer and the epitaxial growth layer. The superlattice structure includes a plurality of alternately stacked superlattice units, and adjacent two superlattice units include a first superlattice unit and a second superlattice unit. The first superlattice unit includes a first superlattice layer and a second superlattice layer stacked thereon, the second superlattice unit includes a third superlattice layer and a fourth superlattice layer stacked thereon, where each of the first, second, third and fourth superlattice layers includes a plurality of pairs of two sublayers with different compositions from each other.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a gate structure, a first interlayer dielectric layer, a source structure, a drain structure, a dielectric pattern, and first and second field plates. The gate structure is disposed on the substrate. The first interlayer dielectric layer is disposed on the substrate and partially covers the gate structure. The source structure and the drain structure are disposed on the substrate and are located on opposite sides of the gate structure. The dielectric pattern is disposed on the first interlayer dielectric layer between the gate structure and the drain structure. The first field plate covers the dielectric pattern, as well as covering the first interlayer dielectric layer between the gate structure and the dielectric pattern. The second field plate is disposed above the first field plate and the dielectric pattern and extends toward the drain structure.

Abstract: A semiconductor device includes a substrate, a seed layer on the substrate, an epitaxy stack on the seed layer, and a gate structure on the epitaxy stack. The semiconductor device further includes a source structure and a drain structure on opposite sides of the gate structure, respectively. The semiconductor device further includes an isolation region corresponding to an end region of the gate structure. The isolation region is adjacent to the end region of the gate structure. The isolation region is positioned outside the end region of the gate structure. The isolation region is not in contact with the gate structure.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a gate structure, first and second interlayer dielectric layers, a drain structure and a first field plate. The first interlayer dielectric layer partially covers the substrate and the gate structure disposed on the substrate. The drain structure is located on a first side of the gate structure. A drain electrode layer of the drain structure extends from the substrate not covered by the first interlayer dielectric layer to cover a first top surface of the first interlayer dielectric layer. The second interlayer dielectric layer is disposed on the first interlayer dielectric layer and covers the drain electrode layer. The first field plate is disposed on the second interlayer dielectric layer and partially overlaps the drain electrode layer on the first top surface of the first interlayer dielectric layer. The first field plate is electrically floating.

Abstract: A high electron mobility transistor includes a semiconductor channel layer and a semiconductor barrier layer disposed on a substrate. A source electrode, a gate electrode and a drain electrode are disposed on the semiconductor channel layer. A patterned dielectric layer is disposed on the semiconductor barrier layer, and between the gate electrode and the drain electrode. A first field plate is extended continuously from a side of the patterned dielectric layer to the top surface thereof, and has a step in height. A first dielectric layer is disposed between the semiconductor barrier layer and the patterned dielectric layer. A second dielectric layer covers the patterned dielectric layer. The dielectric constant of the patterned dielectric layer is higher than that of the first dielectric layer and the second dielectric layer.

Abstract: A semiconductor structure includes a nucleation layer disposed on a substrate, an epitaxial growth layer disposed above the nucleation layer, and a superlattice structure disposed between the nucleation layer and the epitaxial growth layer. The superlattice structure includes a plurality of alternately stacked superlattice units, and adjacent two superlattice units include a first superlattice unit and a second superlattice unit. The first superlattice unit includes a first superlattice layer and a second superlattice layer stacked thereon, the second superlattice unit includes a third superlattice layer and a fourth superlattice layer stacked thereon, where each of the first, second, third and fourth superlattice layers includes a plurality of pairs of two sublayers with different compositions from each other.

Abstract: A wideband impedance matching network comprises a fundamental output MN including a first portion and a second portion and a harmonic compensation MN including a harmonic MN portion and a harmonic MN backside-via inductor formed on an outer surface of a harmonic MN backside via hole penetrating through a semiconductor substrate. The first portion, the second portion and the harmonic MN portion are formed on the semiconductor substrate. A second terminal of the first portion and a first terminal of the second portion are connected to an RF output terminal. A first terminal of the harmonic MN portion and a first terminal of the first portion are connected to an RF input terminal. A second terminal of the harmonic MN portion is connected to a first terminal of the harmonic MN backside-via inductor. A second terminal of the harmonic MN backside-via inductor is grounded.

Abstract: An ohmic metal for GaN device comprises a diffusion barrier seed metal layer and a plurality of metal layers. The diffusion barrier seed metal layer is formed on an epitaxial structure layer. The diffusion barrier seed metal layer is made of Pt. The epitaxial structure layer is made of AlGaN or GaN. The plurality of metal layers is formed on the diffusion barrier seed metal layer. The plurality of metal layers comprises a first metal layer and a second metal layer. The first metal layer is formed on the diffusion barrier seed metal layer. The first metal layer is made of Ti. The second metal layer is formed on the first metal layer. The second metal layer is made of Al. By the diffusion barrier seed metal layer, so as to suppress the diffusion of the plurality of metal layers into the epitaxial structure layer.

Abstract: An ohmic metal for GaN device comprises a diffusion barrier seed metal layer and a plurality of metal layers. The diffusion barrier seed metal layer is formed on an epitaxial structure layer. The diffusion barrier seed metal layer is made of Pt. The epitaxial structure layer is made of AlGaN or GaN. The plurality of metal layers is formed on the diffusion barrier seed metal layer. The plurality of metal layers comprises a first metal layer and a second metal layer. The first metal layer is formed on the diffusion barrier seed metal layer. The first metal layer is made of Ti. The second metal layer is formed on the first metal layer. The second metal layer is made of Al. By the diffusion barrier seed metal layer, so as to suppress the diffusion of the plurality of metal layers into the epitaxial structure layer.

Abstract: A radio frequency (RF) power transistor includes a semiconductor heterostructure, a gate electrode, a drain electrode and a source electrode. The drain electrode includes an ohmic contact and a Schottky contact extending from the ohmic contact toward the gate electrode, spaced apart from the gate electrode (4) by a distance (LGD), and having a length (LEXT) being not less than 2 ?m and not greater than 4 ?m. A ratio of the length (LEXT) to a sum of the length (LEXT) and a distance (LGD) is greater than 0.83 and less than 0.98.

Abstract: A radio frequency (RF) power transistor includes a semiconductor heterostructure, a gate electrode, a drain electrode and a source electrode. The drain electrode includes an ohmic contact and a Schottky contact extending from the ohmic contact toward the gate electrode, spaced apart from the gate electrode (4) by a distance (LGD), and having a length (LEXT) being not less than 2 ?m and not greater than 4 ?m. A ratio of the length (LEXT) to a sum of the length (LEXT) and a distance (LGD) is greater than 0.83 and less than 0.98.

Abstract: A radio frequency (RF) power transistor includes: a semiconductor heterostructure that includes an undoped barrier layer and an active layer and that is formed with a continuous two dimensional electron gas (2DEG) channel having an ohmic source-aligned region, an ohmic drain-aligned region and a Schottky-aligned region; agate electrode; and source and drain electrodes. One of the source and drain electrodes includes an ohmic contact and a Schottky contact that extends from the ohmic contact toward the gate electrode. The 2DEG channel is normally on and extends continuously from the ohmic source-aligned region to the ohmic drain-aligned region. The Schottky contact overlaps and is capacitively coupled to the Schottky-aligned region of the 2DEG channel.

Abstract: A semiconductor is fabricated on a silicon (Si) substrate. The semiconductor is III-nitride based. The Si substrate is partially isolated. Etching is directly processed from top on a chip for solving wire-width problem. The Si substrate does not need to be made thin. The chip can be large scaled and be prevented from bowing. Thus, the present invention simplifies producing procedure and reduces production cost. Besides, for a large-scaled chip, the breakdown voltage is enhanced; and, without making the Si substrate thin, the on-state current is remained the same and the heat problem is weakened.

Abstract: A semiconductor is fabricated on a silicon (Si) substrate. The semiconductor is III-nitride based. The Si substrate is partially isolated. Etching is directly processed from top on a chip for solving wire-width problem. The Si substrate does not need to be made thin. The chip can be large scaled and be prevented from bowing. Thus, the present invention simplifies producing procedure and reduces production cost. Besides, for a large-scaled chip, the breakdown voltage is enhanced; and, without making the Si substrate thin, the on-state current is remained the same and the heat problem is weakened.