Patents by Inventor Yi-Wen PAN

Yi-Wen PAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12278176
    Abstract: An integrated circuit structure includes a substrate, a transistor, a first dielectric layer, a metal contact, a first low-k dielectric layer, a second dielectric layer, and a first metal feature. The transistor is over the substrate. The first dielectric layer is over the transistor. The metal contact is in the first dielectric layer and electrically connected to the transistor. The first low-k dielectric layer is over the first dielectric layer. The second dielectric layer is over the first low-k dielectric layer and has a dielectric constant higher than a dielectric constant of the first low-k dielectric layer. The first metal feature extends through both second dielectric layer and the first low-k dielectric layer to the metal contact.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: April 15, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Wen Pan, Chung-Chi Ko
  • Publication number: 20240395699
    Abstract: An integrated circuit structure includes a substrate, a transistor, a first dielectric layer, a metal contact, a first low-k dielectric layer, a second dielectric layer, and a first metal feature. The transistor is over the substrate. The first dielectric layer is over the transistor. The metal contact is in the first dielectric layer and electrically connected to the transistor. The first low-k dielectric layer is over the first dielectric layer. The second dielectric layer is over the first low-k dielectric layer and has a dielectric constant higher than a dielectric constant of the first low-k dielectric layer. The first metal feature extends through both second dielectric layer and the first low-k dielectric layer to the metal contact.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Wen PAN, Chung-Chi KO
  • Publication number: 20240387384
    Abstract: A method includes depositing a dielectric layer over a substrate, and etching the dielectric layer to form an opening and to expose a first conductive feature underlying the dielectric layer. The dielectric layer is formed using a precursor including nitrogen therein. The method further includes depositing a sacrificial spacer layer extending into the opening, and patterning the sacrificial spacer layer to remove a bottom portion of the sacrificial spacer layer. A vertical portion of the sacrificial spacer layer in the opening and on sidewalls of the dielectric layer is left to form a ring. A second conductive feature is formed in the opening. The second conductive feature is encircled by the ring, and is over and electrically coupled to the first conductive feature. At least a portion of the ring is removed to form an air spacer.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Ming-Tsung Lee, Yi-Wen Pan, Tzu-Nung Lu, You-Lan Li, Chung-Chi Ko
  • Publication number: 20240153814
    Abstract: Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming an interconnect structure over a substrate. The forming the interconnect structure over the semiconductor device structure includes forming a dielectric layer, then performing an annealing process, then forming one or more openings in the dielectric layer, then performing a first ultraviolet (UV) curing process, and then forming conductive features in the one or more openings.
    Type: Application
    Filed: January 6, 2024
    Publication date: May 9, 2024
    Inventors: Yi-Wen PAN, You-Lan LI, Chung-Chi KO
  • Patent number: 11901219
    Abstract: Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming an interconnect structure over a substrate. The forming the interconnect structure over the semiconductor device structure includes forming a dielectric layer, then performing an annealing process, then forming one or more openings in the dielectric layer, then performing a first ultraviolet (UV) curing process, and then forming conductive features in the one or more openings.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Wen Pan, You-Lan Li, Chung-Chi Ko
  • Publication number: 20230154852
    Abstract: A method includes depositing a dielectric layer over a substrate, and etching the dielectric layer to form an opening and to expose a first conductive feature underlying the dielectric layer. The dielectric layer is formed using a precursor including nitrogen therein. The method further includes depositing a sacrificial spacer layer extending into the opening, and patterning the sacrificial spacer layer to remove a bottom portion of the sacrificial spacer layer. A vertical portion of the sacrificial spacer layer in the opening and on sidewalls of the dielectric layer is left to form a ring. A second conductive feature is formed in the opening. The second conductive feature is encircled by the ring, and is over and electrically coupled to the first conductive feature. At least a portion of the ring is removed to form an air spacer.
    Type: Application
    Filed: February 22, 2022
    Publication date: May 18, 2023
    Inventors: Ming-Tsung Lee, Yi-Wen Pan, Tzu-Nung Lu, You-Lan Li, Chung-Chi Ko
  • Publication number: 20230057914
    Abstract: Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming an interconnect structure over a substrate. The forming the interconnect structure over the semiconductor device structure includes forming a dielectric layer, then performing an annealing process, then forming one or more openings in the dielectric layer, then performing a first ultraviolet (UV) curing process, and then forming conductive features in the one or more openings.
    Type: Application
    Filed: August 19, 2021
    Publication date: February 23, 2023
    Inventors: Yi-Wen PAN, You-Lan LI, Chung-Chi KO
  • Publication number: 20220359376
    Abstract: An integrated circuit structure includes a substrate, a transistor, a first dielectric layer, a metal contact, a first low-k dielectric layer, a second dielectric layer, and a first metal feature. The transistor is over the substrate. The first dielectric layer is over the transistor. The metal contact is in the first dielectric layer and electrically connected to the transistor. The first low-k dielectric layer is over the first dielectric layer. The second dielectric layer is over the first low-k dielectric layer and has a dielectric constant higher than a dielectric constant of the first low-k dielectric layer. The first metal feature extends through both second dielectric layer and the first low-k dielectric layer to the metal contact.
    Type: Application
    Filed: October 1, 2021
    Publication date: November 10, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Wen PAN, Chung-Chi KO