Patents by Inventor Yi WONG
Yi WONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210043549Abstract: A clip for a semiconductor package includes a first portion and a second portion. The first portion includes a first surface, a second surface opposite to the first surface and configured to contact a first electrically conductive component, and a stepped region between the first surface and the second surface such that the second surface has a smaller area than the first surface. The second portion is coupled to the first portion and configured to contact a second electrically conductive component. The second portion includes a third surface aligned with the first surface.Type: ApplicationFiled: August 8, 2019Publication date: February 11, 2021Applicant: Infineon Technologies AGInventors: Ke Yan Tean, Mei Fen Hiew, Jia Yi Wong
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Patent number: 10727151Abstract: A semiconductor chip package includes an electrically conducting carrier and a semiconductor chip disposed over the electrically conducting carrier. The semiconductor chip has a first surface facing the electrically conducting carrier and a second surface opposite the first surface. A metal plate has a first surface mechanically connected to the second surface of the semiconductor chip and a second surface opposite the first surface of the metal plate. The metal plate completely overlaps the second surface of the semiconductor chip. The second surface of the metal plate is at least partially exposed at a periphery of the semiconductor chip package.Type: GrantFiled: May 25, 2017Date of Patent: July 28, 2020Assignee: Infineon Technologies AGInventors: Liu Chen, Teck Sim Lee, Jia Yi Wong, Wei Han Koo, Thomas Stoeck, Gilles Delarozee
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Publication number: 20200111750Abstract: A semiconductor device and method is disclosed. The semiconductor device may include a semiconductor substrate including an active area, a metal layer structure over the active area, wherein the metal layer structure is configured to form an electrical contact, the metal layer structure including a solder area, a buffer area, and a barrier area between the solder area and the buffer area, wherein, in the barrier area, the metal layer structure is further away from the active area than in the solder area and in the buffer area, and wherein each of the solder area and the buffer area is in direct contact with the active area or with a wiring layer structure arranged between the active area and the metal layer structure.Type: ApplicationFiled: October 3, 2019Publication date: April 9, 2020Applicant: Infineon Technologies AGInventors: Stefan Beyer, Marius Aurel Bodea, Jia Yi Wong
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Patent number: 10431526Abstract: A metal heat slug having an upper and lower surface is provided. First and second electrically conductive leads are provided. First and second electrically insulating fastening mechanisms are provided. The first and second fastening mechanisms are adhered to the upper surface of the heat slug in an outer peripheral region of the heat slug such that the first and second leads are vertically separated from and electrically insulated from the heat slug. The central die attach region is exposed from the first and second fastening mechanisms after adhering the first and second fastening mechanisms to the upper surface of the heat slug.Type: GrantFiled: October 9, 2017Date of Patent: October 1, 2019Assignee: Cree, Inc.Inventors: Kar Meng Ho, Chiew Li Tai, Jia Yi Wong, Sanjay Kumar Murugan
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Publication number: 20190109070Abstract: A metal heat slug having an upper and lower surface is provided. First and second electrically conductive leads are provided. First and second electrically insulating fastening mechanisms are provided. The first and second fastening mechanisms are adhered to the upper surface of the heat slug in an outer peripheral region of the heat slug such that the first and second leads are vertically separated from and electrically insulated from the heat slug. The central die attach region is exposed from the first and second fastening mechanisms after adhering the first and second fastening mechanisms to the upper surface of the heat slug.Type: ApplicationFiled: October 9, 2017Publication date: April 11, 2019Inventors: Kar Meng Ho, Chiew Li Tai, Jia Yi Wong, Sanjay Kumar Murugan
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Publication number: 20180358287Abstract: An electronic device and method is disclosed. In one example, the electronic device includes a semiconductor chip and a leadframe. The leadframe includes a first class of leads and a second class of leads. The leads of the second class of leads are thinner than leads of the first class of leads.Type: ApplicationFiled: June 13, 2018Publication date: December 13, 2018Applicant: Infineon Technologies AGInventors: Jia Yi Wong, Kar Meng Ho
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Publication number: 20180342438Abstract: A semiconductor chip package includes an electrically conducting carrier and a semiconductor chip disposed over the electrically conducting carrier. The semiconductor chip has a first surface facing the electrically conducting carrier and a second surface opposite the first surface. A metal plate has a first surface mechanically connected to the second surface of the semiconductor chip and a second surface opposite the first surface of the metal plate. The metal plate completely overlaps the second surface of the semiconductor chip. The second surface of the metal plate is at least partially exposed at a periphery of the semiconductor chip package.Type: ApplicationFiled: May 25, 2017Publication date: November 29, 2018Inventors: Liu Chen, Teck Sim Lee, Jia Yi Wong, Wei Han Koo, Thomas Stoek, Gilles Delarozee
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Patent number: 10121848Abstract: A method for fabricating a multi-layer, crown-shaped MIM capacitor is provided. A base having therein a conductive region within a capacitor-forming region is formed. An IMD layer is deposited on the base to cover the capacitor-forming region. A capacitor trench is formed within the capacitor-forming region. The capacitor trench penetrates through the IMD layer, thereby exposing a portion of the conductive region. A concentric capacitor lower electrode structure is formed within the capacitor trench. The concentric capacitor lower electrode structure includes a first electrode and a second electrode surrounded by the first electrode. The first electrode is in direct contact with the conductive region. A conductive supporting pedestal is formed within the capacitor trench for fixing and electrically connecting bottom portions of the first and second electrodes. A capacitor dielectric layer conformally lining the first and second electrodes and a top surface of the conductive supporting pedestal is formed.Type: GrantFiled: May 14, 2017Date of Patent: November 6, 2018Assignee: Powerchip Technology CorporationInventors: Shyng-Yeuan Che, Wen-Yi Wong
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Publication number: 20170250245Abstract: A method for fabricating a multi-layer, crown-shaped MIM capacitor is provided. A base having therein a conductive region within a capacitor-forming region is formed. An IMD layer is deposited on the base to cover the capacitor-forming region. A capacitor trench is formed within the capacitor-forming region. The capacitor trench penetrates through the IMD layer, thereby exposing a portion of the conductive region. A concentric capacitor lower electrode structure is formed within the capacitor trench. The concentric capacitor lower electrode structure includes a first electrode and a second electrode surrounded by the first electrode. The first electrode is in direct contact with the conductive region. A conductive supporting pedestal is formed within the capacitor trench for fixing and electrically connecting bottom portions of the first and second electrodes. A capacitor dielectric layer conformally lining the first and second electrodes and a top surface of the conductive supporting pedestal is formed.Type: ApplicationFiled: May 14, 2017Publication date: August 31, 2017Inventors: Shyng-Yeuan Che, Wen-Yi Wong
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Patent number: 9735228Abstract: A multi-layer, crown-shaped MIM capacitor includes a base having therein conductive region, an inter-metal dielectric (IMD) layer on the base, a capacitor trench penetrating through the IMD layer and exposing the conductive region, a capacitor lower electrode structure including a first electrode and a second electrode surrounded by the first electrode, a conductive supporting pedestal within the capacitor trench for fixing and electrically connecting the bottom portions of the first and second electrodes, a capacitor dielectric layer conformally lining the first and second electrodes and a top surface of the conductive supporting pedestal, and a capacitor upper electrode on the capacitor dielectric layer.Type: GrantFiled: January 3, 2016Date of Patent: August 15, 2017Assignee: Powerchip Technology CorporationInventors: Shyng-Yeuan Che, Wen-Yi Wong
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Publication number: 20170069710Abstract: A multi-layer, crown-shaped MIM capacitor includes a base having therein conductive region, an inter-metal dielectric (IMD) layer on the base, a capacitor trench penetrating through the IMD layer and exposing the conductive region, a capacitor lower electrode structure including a first electrode and a second electrode surrounded by the first electrode, a conductive supporting pedestal within the capacitor trench for fixing and electrically connecting the bottom portions of the first and second electrodes, a capacitor dielectric layer conformally lining the first and second electrodes and a top surface of the conductive supporting pedestal, and a capacitor upper electrode on the capacitor dielectric layer.Type: ApplicationFiled: January 3, 2016Publication date: March 9, 2017Inventors: Shyng-Yeuan Che, Wen-Yi Wong
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Patent number: 9418569Abstract: There are provided methods and a system for visually representing a rate of writing a plurality of identical Chinese characters for at least one user on a first portion of a display, with the visual representation having both a discrete movement component and a rate of activity component.Type: GrantFiled: December 22, 2010Date of Patent: August 16, 2016Assignee: Creative Technology LtdInventors: Wong Hoo Sim, Kin Fui Chong, Xin Yi Wong
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Publication number: 20150371862Abstract: A method of forming a pattern including following steps is provided. A wafer is provided, wherein the wafer includes a plurality of wafer interior dies and a plurality of wafer edge dies. A first pattern is formed on each of the wafer interior dies, and a second pattern is formed on each of the wafer edge dies. A method of forming the first patterns includes performing at least two exposure processes, and a method of forming the second patterns includes performing at least one of the at least two exposure processes, wherein a number of the exposure processes performed for forming the second patterns is less than a number of the exposure processes performed for forming the first patterns.Type: ApplicationFiled: September 26, 2014Publication date: December 24, 2015Inventors: Wen-Yi Wong, Tuz-Wen Weng
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Patent number: 9156814Abstract: The present invention relates to methods of detecting and monitoring aggregation of beta-amyloid peptides which are associated with neurodegenerative diseases as well as treating and/or preventing the neurodegenerative diseases by using carbazole-based fluorophores. In particular, the present invention provides methods for labeling and imaging the beta-amyloid (A?) peptides, oligomers, and fibrils in vitro and/or in vivo, as well as treating and/or preventing Alzheimer's disease by using the carbazole-based fluorophores of the present invention.Type: GrantFiled: April 13, 2012Date of Patent: October 13, 2015Assignee: HONG KONG BAPTIST UNIVERSITYInventors: Wanggui Yang, Yi Wong, Olivia T. W. Ng, Hung Wing Li, Ken K. L. Yung, Daniel W. J. Kwong, Ricky M. S. Wong
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Patent number: 9096831Abstract: A method is provided to functionally select cells with enhanced characteristics relevant to cell engraftment, including both spontaneous migration and directional migration towards specific chemo-attractants. The cells are preferably undifferentiated cells, such as mesenchymal stem cells. The method involves entrapping or encapsulating the cells in a biomaterial barrier, optionally inducing cell migration, and selecting cells that migrated through the barrier. The cells selected by this method have better migratory activities and enhanced in vivo engraftment to injured tissues when they are supplemented systemically.Type: GrantFiled: June 14, 2011Date of Patent: August 4, 2015Assignee: Versitech LimitedInventors: Barbara Pui Chan, Hoi Ling Wong, Mei Yi Wong, Godfrey Chi-Fung Chan, Zhen Fan Yang
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Patent number: 8889754Abstract: The invention provides a cellular polyurethane foam composition for forming a cellular ceramic under fire conditions, the composition comprising: at least 40% by weight based on the total weight of the composition of a polyurethane; from 10% to 40% by weight based on the total weight of the composition of silicate mineral filler; from 5% to 20% by weight based on the total weight of the composition of at least one inorganic phosphate that forms a liquid phase at a temperature of no more than 800° C.; from 0.1% to 10% by weight based on the total weight of the composition of a heat expandable solid material; and wherein the total proportion of inorganic components constitutes in the range of from 20% to 60% by weight of the total composition.Type: GrantFiled: May 5, 2008Date of Patent: November 18, 2014Assignee: Polymers CRC LtdInventors: Pulahinge Don Dayananda Rodrigo, Susan Wan Yi Wong, Yi-Bing Cheng, Kevin William Thomson, Robert Arthur Shanks, Vanja Pasanovic-Zujo
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Patent number: 8877617Abstract: A method for forming of a thin film on a substrate is disclosed. The method includes cleaning a process chamber by flowing a first gas having fluorine. The method also includes coating the process chamber with a first encapsulating layer including amorphous silicon (A-Si) by flowing a second gas for a first duration, where the first encapsulating layer protects against fluorine contamination. The method further includes loading a substrate into the process chamber, depositing a thin film on the substrate by flowing a third gas into the process chamber and unloading the substrate from the process chamber. The thin film can include silicon nitride (SiN), the first gas can include nitrogen triflouride (NF3) gas and second gas can include silane (SiH4) gas. The thin film can be formed using plasma-enhanced chemical vapor deposition. The substrate can be a solar cell or a liquid crystal display (LCD).Type: GrantFiled: September 27, 2012Date of Patent: November 4, 2014Assignee: SunPower CorporationInventors: Jia Yi Wong, Thomas Qiu
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Publication number: 20140044727Abstract: The present invention is directed to a method for reducing the viscosity of a formulation containing acetate and a therapeutic protein and formulations made using the claimed method.Type: ApplicationFiled: April 6, 2012Publication date: February 13, 2014Applicant: Glaxosmithkline LLCInventors: Myrna A. Monck, Man Yi Wong, Kai Zhang
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Publication number: 20140023655Abstract: The present invention is directed to a method for reducing the viscosity of a formulation containing citrate and a therapeutic protein and formulations made using the claimed method.Type: ApplicationFiled: April 6, 2012Publication date: January 23, 2014Applicant: Glaxosmithkline LLCInventors: Myrna A. Monck, Man Yi Wong, Kai Zhang
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Patent number: 8487798Abstract: A synthesis method of Sigma-Delta modulator capable of relaxing circuit specification and reducing power consumption, comprising the following steps: firstly, set a target bandwidth and a target performance; upon obtaining a Noise Transfer Function (NTF), perform coefficient synthesis a first time, to ascertain a plurality sets of first performance results corresponding to said NTF, and obtain a plurality sets of first circuit specifications fulfilling said target performance, through analyzing circuit non-ideal effect of said first performance results. Next, increase an oversampling ratio of parameters, to obtain a plurality sets of second performance results, and a plurality sets of second circuit specifications. Then, increase quantizer bit number, and increase attenuation quantity, to obtain a plurality sets of third circuit specifications. Finally, compare said first, second and third circuit specifications, to select one of greatest variation to perform calibrations.Type: GrantFiled: March 23, 2012Date of Patent: July 16, 2013Assignee: National Chung Cheng UniversityInventors: Shuenn-Yuh Lee, Jia-Hua Hong, Jing-Yi Wong