Patents by Inventor Yi-Yeh Chuang

Yi-Yeh Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240081056
    Abstract: A double patterning method of manufacturing select gates and word lines is provided in the present invention, including forming first string patterns composed of word line patterns and select gate patterns on a target layer, forming a conformal spacer layer on first string patterns, wherein the spacer layer forms trenches between first string patterns, forming a fill layer filling up the trenches on the spacer layer, removing fill layer outside of the trenches, so that fill layer in the trenches forms second string patterns, wherein the second string patterns and the first string patterns are spaced apart, removing exposed spacer layer, so that the first string patterns and the second string patterns constitute target patterns spaced apart from each other on the target layer, and performing an etching process using those target patterns as a mask to remove exposed target layer, so as to form word lines and select gates.
    Type: Application
    Filed: April 25, 2023
    Publication date: March 7, 2024
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Yi-Yeh Chuang, Zih-Song Wang, Li-Ta Chen, Shun-Yu Gao