Abstract: A semiconductor structure includes a first upper source/drain region, a second upper source/drain region, a first lower source/drain contact, a second lower source/drain contact, and a third conductive region. The first upper source/drain contact is disposed at a first elevation. The second upper source/drain contact is disposed at the first elevation. The first lower source/drain contact is disposed at a second elevation. The second lower source/drain contact is disposed at the second elevation. The third conductive region is disposed at a third elevation. A projection area of the third conductive region is disposed between a projection area of the first upper source/drain contact and a projection area of the second upper source/drain contact. The third elevation is disposed between the first elevation and the second elevation.

Abstract: An integrated circuit device includes first and second stack structures and a side connection structure. The first stack structure includes a first transistor and a second transistor stacked thereon. The second stack structure includes a third transistor and a fourth transistor stacked thereon. Each of the first to fourth transistors includes an active layer having a channel region and a source/drain region, a gate structure wrapping around the channel region, and a source/drain contact surrounding the source/drain region. The active layer and the side connection structure extend substantially along a first direction in a top view, and the gate structure extends substantially along a second direction orthogonal to the first direction in the top view. The side connection structure electrically connects one of the source/drain contact and the gate structure of the first transistor to one of the source/drain contact and the gate structure of the third transistor.

Abstract: An integrated circuit includes a first-type active-region structure and a second-type active-region structure extending in a first direction and a first terminal-conductor and a second terminal-conductor extending in a second direction. The integrated circuit also includes a first power stub and a second power stub in a first metal layer and a first power line and a second power line in a second metal layer. The integrated circuit further includes a first via connector directly connected between the first power stub and the first terminal-conductor, a second via connector directly connected between the second power stub and the second terminal-conductor, a third via connector directly connected between the first power stub and the first power line, and a fourth via connector directly connected between the second power stub and the second power line.

Abstract: A semiconductor structure includes a first transistor, a second transistor, a gate structure, and a gate isolation. The first transistor is of a first conductivity type and comprises a first active region structure. The second transistor is of a second conductivity type different from the first conductivity type and comprises a second active region structure. The second transistor is disposed above the first transistor. The gate structure comprises a first gate connection contacting the first active region structure and a second gate connection contacting the second active region structure. The gate isolation is disposed between the first gate connection and the second gate connection.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device has a cell. The cell includes a gate structure, a first active region, a second active region, a first signal line, and a second signal line. The gate structure extends along a first direction. The first active region extends along a second direction different from the first direction and intersects the gate structure. The second active region extends along the second direction and intersects the gate structure. The first active region overlaps the second active region along a third direction different from the first direction and the second direction. The first signal line is over the first active region and configured to transmit an input signal. The second signal line is under the second active region and configured to transmit an output signal.

Abstract: An electronic device including a first electronic element, a second electronic element, a first signal track, and a second signal track is provided. The second electronic element is different from the first electronic element. The first signal track is electrically connected to the first electronic element. The second signal track is electrically connected to the second electronic element and electrically separated from the first signal track. A width of the second signal track is substantially 8˜100 nm. The first signal track has a larger cross-sectional area than the second signal track.

Abstract: A cell region (of a device) includes: a first active region (AR); first MD structures aligning to beta tracks; and in a first metallization layer, segments aligning to alpha tracks. For one or more first or second locations, a corresponding region of the first AR is configurable as a source region or a drain region. For one or more third locations, a corresponding region of the first AR is configurable as a source region, but not as a drain region. For one or more fourth locations, a corresponding region of the AR is not configurable as a source region or a drain region. Each of the first to fourth locations is at an intersection of a corresponding alpha track and a corresponding beta track.

Abstract: An integrated circuit includes a first and second active region, a first and second contact, a first conductor and a first insulating region. The first active region extends in a first direction, is on a first level above a front-side of a substrate, and corresponds to a first set of transistors. The second active region extends in the first direction, is on a second level, and corresponds to a second set of transistors. The first contact extends in a second direction, is on a third level, and overlaps the first active region. The second contact extends in the second direction, is on a fourth level, overlaps the second active region. The first conductor extends in the first direction, is on the third level and the fourth level, and is coupled to the first contact and the second contact. The first insulating region is within a recess of the first conductor.

Abstract: An embodiment semiconductor structure includes a first active region and a second active region extending along a first direction, a functional gate structure and a non-functional gate structure aligned with each other and extending along a second direction, and a metallization layer over the functional gate structure and the non-functional gate structure. The metallization layer defines a first metallization region, a second metallization region, and one or two middle metallization regions between the first metallization region and the second metallization region. The functional gate structure overlaps the first metallization region and overlaps one of the one or two middle metallization regions to define an overlapped portion of the one of the one or two middle metallization regions. The overlapped portion has a space defined therein sized for a connection feature between the functional gate structure and the one of the one or two middle metallization regions.

Abstract: An integrated circuit includes a plurality of cells abutted to one another, each of the plurality of cells corresponding to a respective circuit component. Each of the plurality of cells includes: a plurality of active regions extending along a first lateral direction; a plurality of gate structures extending along a second lateral direction perpendicular to the first lateral direction and traversing one or more of the plurality of active regions; a plurality of first interconnect structures extending along the first lateral direction and vertically disposed above the plurality of gate structure; and a plurality of second interconnect structures extending along the second lateral direction and vertically disposed above the plurality of first interconnect structures. Each of the plurality of second interconnect structures is shifted from a corresponding one of the plurality of gate structures with a distance along the first lateral direction.

Abstract: The present application provides a method of processing a substrate. The method of processing the substrate includes steps of forming a photosensitive layer on the substrate; performing a first exposure process to expose the photosensitive layer to actinic radiation through a first mask; performing a first developing process to remove portions of the photosensitive layer exposed to the actinic radiation and form an intermediate pattern; performing a second exposure process to expose the intermediate pattern to the actinic radiation through a second mask; performing a second developing process to remove portions of the intermediate pattern shielded from the actinic radiation and form a target pattern; and performing an etching process to remove portions of the substrate exposed by the target pattern.

Abstract: The present application provides a method of processing a substrate and a method of fabricating bit line contacts over the substrate. The method of processing the substrate includes steps of forming a photosensitive layer on the substrate; performing a first exposure process to expose the photosensitive layer to actinic radiation through a first mask; performing a first developing process to remove portions of the photosensitive layer exposed to the actinic radiation and form an intermediate pattern; performing a second exposure process to expose the intermediate pattern to the actinic radiation through a second mask; performing a second developing process to remove portions of the intermediate pattern shielded from the actinic radiation and form a target pattern; and performing an etching process to remove portions of the substrate exposed by the target pattern.

Abstract: A integrated circuit includes a first, a second, a third, and a fourth gate, a first input pin and a first conductor. The first and third gate are on a first level. The second and fourth gate are on a second level. The second gate is coupled to the first gate. The fourth gate is coupled to the third gate. The first input pin extends in a second direction, is on a first metal layer above a front-side of a substrate, is coupled to the first gate, and configured to receive a first input signal. The first input pin is electrically coupled to the third gate by the first, second or fourth gate. The first conductor extends in the first direction, is on a second metal layer below a back-side of the substrate, and is coupled to the second and fourth gate.

Abstract: A device including a first vertical field effect transistor having a first drain/source region and a second drain/source region, and a second vertical field effect transistor having a third drain/source region and a fourth drain/source region. The device including a first power contact situated on a frontside of the device and coupled to the first drain/source region, a second power contact situated on the frontside of the device and coupled to the third drain/source region, and a contact situated on a backside of the device and coupled to the second drain/source region and to the fourth drain/source region.

Abstract: An integrated circuit includes a first-type active-region structure and a second-type active-region structure extending in a first direction and a first terminal-conductor and a second terminal-conductor extending in a second direction. The integrated circuit also includes a first power stub and a second power stub in a first metal layer and a first power line and a second power line in a second metal layer. The integrated circuit further includes a first via connector directly connected between the first power stub and the first terminal-conductor, a second via connector directly connected between the second power stub and the second terminal-conductor, a third via connector directly connected between the first power stub and the first power line, and a fourth via connector directly connected between the second power stub and the second power line.

Abstract: A semiconductor structure includes a first upper source/drain region, a second upper source/drain region, a first lower source/drain contact, a second lower source/drain contact, and a third conductive region. The first upper source/drain contact is disposed at a first elevation. The second upper source/drain contact is disposed at the first elevation. The first lower source/drain contact is disposed at a second elevation. The second lower source/drain contact is disposed at the second elevation. The third conductive region is disposed at a third elevation. A projection area of the third conductive region is disposed between a projection area of the first upper source/drain contact and a projection area of the second upper source/drain contact. The third elevation is disposed between the first elevation and the second elevation.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a contact structure, a first conductive element, and a first dielectric spacer structure. The semiconductor substrate includes an active region and an isolation structure. The contact structure is on the active region of the semiconductor substrate. The first conductive element is on the isolation structure of the semiconductor substrate. The first dielectric spacer structure is between the contact structure and the first to conductive element. The first dielectric spacer structure has a first concave surface facing the first conductive element.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a semiconductor substrate including an active region and an isolation structure. The method also includes forming a contact structure on the active region of the semiconductor substrate. The method further includes forming a dielectric spacer on opposite sides of the contact structure. The method also includes forming a conductive element on the isolation structure of the semiconductor substrate, wherein the dielectric spacer has a concave surface facing the conductive element.

Abstract: The present application provides a method of fabricating bit line contacts. The method includes steps of depositing an insulative layer and a sacrificial layer on the substrate; forming a photosensitive layer on the sacrificial layer; performing a first exposure process to expose the photosensitive layer to actinic radiation through a first mask; performing a first developing process to form an intermediate pattern on the sacrificial layer; performing a second exposure process to expose the intermediate pattern to the actinic radiation through a second mask; performing a second developing process to form a target pattern on the sacrificial layer; performing a first etching process to remove portions of the sacrificial layer exposed by the target pattern; performing a second etching process to form a plurality of trenches in the insulative layer; and depositing a conductive material into the plurality of trenches to form the bit line contacts.

Abstract: The present application provides a method of processing a substrate. The method of processing the substrate includes steps of forming a photosensitive layer on the substrate; performing a first exposure process to expose the photosensitive layer to actinic radiation through a first mask; performing a first developing process to remove portions of the photosensitive layer exposed to the actinic radiation and form an intermediate pattern; performing a second exposure process to expose the intermediate pattern to the actinic radiation through a second mask; performing a second developing process to remove portions of the intermediate pattern shielded from the actinic radiation and form a target pattern; and performing an etching process to remove portions of the substrate exposed by the target pattern.