Abstract: A method for forming MOS transistor with improved resistance to HF attack during a pre-SEG clean process is disclosed. The MOS transistor encompasses a substrate having a gate with sidewalls. The gate is patterned on the main surface of the substrate. Source/drain doping regions are formed on opposite sides of the gate electrode in the main surface of the semiconductor substrate. A gate oxide layer is disposed underneath the gate electrode. A surface-nitridized silicon oxide liner covers the two sidewalls of the gate electrode. The surface nitridized silicon oxide liner further overlies lightly doped drain (LDD) regions in close proximity to the gate electrode. A silicon nitride spacer is disposed on the surface-nitridized silicon oxide liner. An elevated selective epitaxial growth (SEG) film is grown on the S/D regions and top of the gate electrode. A silicide layer formed from the elevated SEG film.

Abstract: A metal-oxide-semiconductor (MOS) transistor with improved resistance to HF attack during a pre-SEG clean process is disclosed. The MOS transistor encompasses a semiconductor substrate having a main surface and a gate electrode with two sidewalls. The gate electrode is patterned on the main surface of the semiconductor substrate. Source/drain (S/D) doping regions are formed on opposite sides of the gate electrode in the main surface of the semiconductor substrate. A gate oxide layer is disposed underneath the gate electrode. A surface-nitridized silicon oxide liner covers the two sidewalls of the gate electrode. The surface nitridized silicon oxide liner further overlies lightly doped drain (LDD) regions in close proximity to the gate electrode. A silicon nitride spacer is disposed on the surface-nitridized silicon oxide liner. An elevated selective epitaxial growth (SEG) film is grown on the S/D regions and top of the gate electrode. A silicide layer formed from the elevated SEG film.

Abstract: In the normal fabrication of copper interconnects process, after electro copper deposition (ECD), small copper grains are formed on the surface of copper and the initial grain growth of copper grain is not stable enough and it will grow up in the subsequent unavoidable thermal treatments. Currently, long time low temperature thermal process by furnace is usually adopted to produce a better initial grain growth after electro copper deposition (ECD). However, this long time low temperature thermal process is usually not good enough to stabilize the copper grain in dual damascene structure. In this invention, a fabrication process by adding an extra thermal treatment of short time high temperature processes is used to saturate copper grain growth in copper via holes. By doing this extra thermal step, the internal stress of copper becomes stable than the stress of that after the long time low temperature thermal treatment. The internal structure of copper will thus attain a more stable stress.