Patents by Inventor Yi-Ying Tsai

Yi-Ying Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955329
    Abstract: A method of forming a semiconductor device includes forming a first conductive feature on a bottom surface of an opening through a dielectric layer. The forming the first conductive feature leaves seeds on sidewalls of the opening. A treatment process is performed on the seeds to form treated seeds. The treated seeds are removed with a cleaning process. The cleaning process may include a rinse with deionized water. A second conductive feature is formed to fill the opening.
    Type: Grant
    Filed: April 28, 2023
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Wei Chang, Min-Hsiu Hung, Chun-I Tsai, Ken-Yu Chang, Yi-Ying Liu
  • Patent number: 11956261
    Abstract: A detection method for a malicious domain name in a domain name system (DNS) and a detection device are provided. The method includes: obtaining network connection data of an electronic device; capturing log data related to at least one domain name from the network connection data; analyzing the log data to generate at least one numerical feature related to the at least one domain name; inputting the at least one numerical feature into a multi-type prediction model, which includes a first data model and a second data model; and predicting whether a malicious domain name related to a malware or a phishing website exists in the at least one domain name by the multi-type prediction model according to the at least one numerical feature.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: April 9, 2024
    Assignee: Acer Cyber Security Incorporated
    Inventors: Chiung-Ying Huang, Yi-Chung Tseng, Ming-Kung Sun, Tung-Lin Tsai
  • Patent number: 11942425
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a contact structure, a first conductive element, and a first dielectric spacer structure. The semiconductor substrate includes an active region and an isolation structure. The contact structure is on the active region of the semiconductor substrate. The first conductive element is on the isolation structure of the semiconductor substrate. The first dielectric spacer structure is between the contact structure and the first to conductive element. The first dielectric spacer structure has a first concave surface facing the first conductive element.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: March 26, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chih-Ying Tsai, Jui-Seng Wang, Yi-Yi Chen
  • Patent number: 11926705
    Abstract: A black matte polyimide film is provided, the black matte polyimide film includes polyimide, carbon black and polyimide fine powder. The polyimide component is obtained by polymerization of a dianhydride and a diamine, followed by chemical cyclization, in which the dianhydride is pyromellitic dianhydride, and the diamine comprises 5˜15 mol % of p-phenylenediamine and 95˜85 mol % of 4,4?-diaminodiphenyl ether; the carbon black is present in an amount of 2 to 8 wt % of the polyimide film; and the polyimide fine powder is present in an amount of 5 to 10 wt % of the polyimide film, such that the black matte polyimide film has a glossiness between 5 and 30 and a thermal expansion coefficient of less than 41 ppm/° C.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: March 12, 2024
    Assignee: TAIMIDE TECHNOLOGY INCORPORATION
    Inventors: Yi-Hsueh Ho, Meng-Ying Tsai
  • Patent number: 10121053
    Abstract: A touch device and a waking up method thereof are provided. The touch device includes a sensing area and a sensing circuit. The sensing area includes sensing areas, and each sub sensing area includes sensing points. In the waking up method, at first, a sensing operation is performed at a first time point and a second time to obtain two total capacitance values of the sensing area at the first time point and the second time point. The scan operation scans a portion of the sensing points of each the sub sensing area, and a number of the portion of the sensing points is smaller than a number of the sensing points in one sub sensing area. Then, a difference between the two total capacitance values is calculated, and the touch device is waken up when the capacitance difference value is greater than a threshold capacitance value.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: November 6, 2018
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Jia-Ming He, Yaw-Guang Chang, Yi-Ying Tsai
  • Publication number: 20180150678
    Abstract: A touch device and a waking up method thereof are provided. The touch device includes a sensing area and a sensing circuit. The sensing area includes sensing areas, and each sub sensing area includes sensing points. In the waking up method, at first, a sensing operation is performed at a first time point and a second time to obtain two total capacitance values of the sensing area at the first time point and the second time point. The scan operation scans a portion of the sensing points of each the sub sensing area, and a number of the portion of the sensing points is smaller than a number of the sensing points in one sub sensing area. Then, a difference between the two total capacitance values is calculated, and the touch device is waken up when the capacitance difference value is greater than a threshold capacitance value.
    Type: Application
    Filed: November 28, 2016
    Publication date: May 31, 2018
    Inventors: Jia-Ming HE, Yaw-Guang CHANG, Yi-Ying TSAI
  • Publication number: 20060040065
    Abstract: A method for surface activation on the metallization of electronic devices is provided. It uses plasma-immersion ion implantation and electroless plating to implant the seeds onto the diffusion barrier layer as catalyst for the electroless Cu plating to accomplish the ULSI interconnect metallization. It achieves electroless Cu plating in the deep 100 nm scaled line-width ULSI interconnect metallization by the Pd plasma implantation catalytic treatment. The method can fill the 100 nm line-width vias and trenches for gaining high quality electroless plated metal interconnects, and substitute for the traditional wet activation by SnCl2 and PdCl2 solution. For the plasma implanted seeds and electroless copper techniques, good Cu step coverage and gap-filling capability are observed in the trench and via metallization process with high adhesive strength. After thermal treatment, no obvious interfacial diffusion induced electric failure is found in the interface of the Cu/(implanted Pd)/TaN/FSG assembly.
    Type: Application
    Filed: August 19, 2004
    Publication date: February 23, 2006
    Inventors: Han-Chang Shih, Jian-Hong Lin, Wei-Jen Hsieh, Yi-Ying Tsai, Uei-Shin Chen