Patents by Inventor Yi-Yu Lin

Yi-Yu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11450661
    Abstract: A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a semiconductor fin, a gate dielectric on sidewalls and a top surface of the semiconductor fin, and a gate electrode over the gate dielectric. The semiconductor fin of the first FinFET and the semiconductor fin of the second FinFET are aligned to a straight line. An isolation region is aligned to the straight line, wherein the isolation region includes a portion at a same level as the semiconductor fins of the first FinFET and the second FinFET. A continuous straight semiconductor strip is overlapped by the semiconductor fins of the first FinFET and the second FinFET. A Shallow Trench Isolation (STI) region is on a side of, and contacts, the semiconductor strip. The isolation region and the first STI region form a distinguishable interface.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Yu Hsu, Yi-Tang Lin, Clement Hsingjen Wann, Chih-Sheng Chang, Wei-Chun Tsai, Jyh-Cherng Sheu, Chi-Yuan Shih
  • Publication number: 20220293773
    Abstract: A method for smoothing a surface of a semiconductor portion is disclosed. In the method, an intentional oxide layer is formed on the surface of the semiconductor portion, a treated layer is formed in the semiconductor portion and inwardly of the intentional oxide layer, and then, the intentional oxide layer and the treated layer are removed to obtain a smoothed surface. The method may also be used for widening a recess in a manufacturing process for a semiconductor structure.
    Type: Application
    Filed: March 11, 2021
    Publication date: September 15, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Hsi YANG, Che-Yu LIN, Yi-Fang PAI, Pei-Ren JENG, Chii-Horng LI, Yee-Chia YEO
  • Publication number: 20220285374
    Abstract: In some embodiments, the present disclosure relates to a memory device including a semiconductor substrate, a first electrode disposed over the semiconductor substrate, a ferroelectric layer disposed between the first electrode and the semiconductor substrate, and a first stressor layer separating the first electrode from the ferroelectric layer. The first stressor layer has a coefficient of thermal expansion greater than that of the ferroelectric layer.
    Type: Application
    Filed: May 3, 2021
    Publication date: September 8, 2022
    Inventors: Bi-Shen Lee, Tzu-Yu Lin, Yi Yang Wei, Hai-Dang Trinh, Hsun-Chung Kuang, Cheng-Yuan Tsai
  • Patent number: 11434129
    Abstract: A semiconductor structure includes: a first device; a second device contacted with the first device, wherein a chamber is formed between the first device and the second device; a first hole disposed in the second device and defined between a first end with a first circumference and a second end with a second circumference; a second hole disposed in the second device and aligned to the first hole; and a sealing object for sealing the second hole. The first end links with the chamber, and the first circumference is different from the second circumference, the second hole is defined between the second end and a third end with a third circumference, and the second circumference and the third circumference are smaller than the first circumference.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Wen Cheng, Yi-Chuan Teng, Cheng-Yu Hsieh, Lee-Chuan Tseng, Shih-Chang Liu, Shih-Wei Lin
  • Publication number: 20220273735
    Abstract: The invention provides a method of increasing an amount of oral immunoglobulin A (IgA) and/or inhibiting oral pathogens in a subject in need thereof, which utilizes a composition including a therapeutically effective amount of probiotics as an effective ingredient. The probiotics include Lactobacillus plantarum LPL28, which can efficiently increase the amount of oral IgA and/or inhibit the oral pathogens, and thus have a potential to prevent teeth cavities and/or periodontal diseases.
    Type: Application
    Filed: October 27, 2021
    Publication date: September 1, 2022
    Inventors: Hsieh-Hsun Ho, Wen-Yang Lin, Yi-Wei Kuo, Yen-Yu Huang, Jia-Hung Lin, Chi-Huei Lin, Cheng-Ruei Liu, Shu-Hui Chen
  • Publication number: 20220278115
    Abstract: Ferroelectric stacks are disclosed herein that can improve retention performance of ferroelectric memory devices. An exemplary ferroelectric stack has a ferroelectric switching layer (FSL) stack disposed between a first electrode and a second electrode. The ferroelectric stack includes a barrier layer disposed between a first FSL and a second FSL, where a first crystalline condition of the barrier layer is different than a second crystalline condition of the first FSL and/or the second FSL. In some embodiments, the first crystalline condition is an amorphous phase, and the second crystalline condition is an orthorhombic phase. In some embodiments, the first FSL and/or the second FSL include a first metal oxide, and the barrier layer includes a second metal oxide. The ferroelectric stack can be a ferroelectric capacitor, a portion of a transistor, and/or connected to a transistor in a ferroelectric memory device to provide data storage in a non-volatile manner.
    Type: Application
    Filed: July 26, 2021
    Publication date: September 1, 2022
    Inventors: Yi Yang Wei, Tzu-Yu Lin, Bi-Shen Lee, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang
  • Patent number: 11430923
    Abstract: An embodiment of the present invention provides a micro light emitting diode (LED) array and its manufacturing method. The micro-LED includes a substrate, an epitaxial layer formed on the substrate, and a conversion film formed on the epitaxial layer. Pixels can be defined through lithography, and the pixel size can be very small. This method is characterized in that a mass transfer is not required.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: August 30, 2022
    Assignee: National Taiwan University
    Inventors: Ching-Fuh Lin, Chun-Yu Lin, Yi-Shan Lin, Jung-Kuan Huang
  • Patent number: 11422330
    Abstract: A driving mechanism for moving an optical element is provided, including a movable portion, a fixed portion, a driving assembly, and a first resilient element. The movable portion is for connecting the optical element. The movable portion is movable relative to the fixed portion. The driving assembly drives the movable portion to move relative to the fixed portion. The first resilient element has a board structure. The movable portion is movably connected to the fixed portion via the first resilient element. The fixed portion includes a connection surface, a restricting surface, and a recessed portion. At least a portion of the first resilient element is disposed on the connection surface. The restricting surface contacts and restricts the movable portion. The recessed portion is located between the connection surface and the restricting surface, wherein the recessed portion is lower than the connection surface and the restricting surface.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: August 23, 2022
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Bing-Ru Song, Yi-Ho Chen, Chia-Pin Hsu, Chih-Wei Weng, Shin-Hua Chen, Chien-Lun Huang, Chao-Chun Chang, Shou-Jen Liu, Kun-Shih Lin, Nai-Wen Hsu, Yu-Cheng Lin, Shang-Yu Hsu, Yu-Huai Liao, Yi-Hsin Nieh, Shih-Ting Huang, Kuo-Chun Kao, Fu-Yuan Wu
  • Publication number: 20220262691
    Abstract: A semiconductor package includes a package substrate having a top surface and a bottom surface, and a stiffener ring mounted on the top surface of the package substrate. The stiffener ring includes a reinforcement rib that is coplanar with the stiffener ring on the top surface of the package substrate. At least two compartments are defined by the stiffener ring and the reinforcement rib. At least two individual chip packages are mounted on chip mounting regions within the at least two compartments, respectively, thereby constituting a package array on the package substrate.
    Type: Application
    Filed: March 2, 2022
    Publication date: August 18, 2022
    Applicant: Media Tek Inc.
    Inventors: Chi-Wen Pan, I-Hsuan Peng, Sheng-Liang Kuo, Yi-Jou Lin, Tai-Yu Chen
  • Publication number: 20220255416
    Abstract: A soft-switching power converter includes a main switch, an energy-releasing switch, and an inductive coupled unit. The main switch is a controllable switch. The energy-releasing switch is coupled to the main switch. The inductive coupled unit is coupled to the main switch and the energy-releasing switch. The inductive coupled unit includes a first inductance, a second inductance coupled to the first inductance, and an auxiliary switch unit. The auxiliary switch unit is coupled to the second inductance to form a closed loop. The main switch and the energy-releasing switch are alternately turned on and turned off. The auxiliary switch unit is controlled to start turning on before the main switch is turned on so as to provide at least one current path.
    Type: Application
    Filed: January 6, 2022
    Publication date: August 11, 2022
    Inventors: Hung-Chieh LIN, Yi-Ping HSIEH, Jin-Zhong HUANG, Hung-Yu HUANG, Chih-Hsien LI, Ciao-Yin PAN
  • Patent number: 11408692
    Abstract: A liquid cooling device includes a liquid cooling conductor, a detecting probe, and a determining circuit. The liquid cooling conductor includes a chamber defined therein for communicating with the outside, the chamber is configured to accommodate the coolant, and the surface of the liquid cooling conductor is provided with at least one communicating port communicating with the chamber; wherein the liquid cooling conductor is formed joining at least two combination blocks, and at least one of the two combination blocks is a metal conductor. The detecting probe is disposed on the liquid cooling conductor and normally electrically disconnected from the metal conductor. The determining circuit is electrically connected to the metal conductor and the detecting probe, and generates a liquid leakage alarm signal when the metal conductor and the detecting probe are electrically connected.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: August 9, 2022
    Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.
    Inventors: Shun-Chih Huang, Tai-Chuan Mao, Ching-Yu Lu, Yi-Jhen Lin, Liang-Yu Wu
  • Patent number: 11406628
    Abstract: Provided is a sustained-release triptan composition as a suitable depot formulation to carry a therapeutically effective amount of triptan for administration via subcutaneous or intramuscular injection. This sustained-release triptan composition is characterized by a high drug to phospholipid ratio and provides an improved pharmacokinetic profile in vivo. The sustained-release triptan composition is for use as a medicament in the treatment of migraine or cluster headache.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 9, 2022
    Assignees: Taiwan Liposome Co., Ltd, TLC Biopharmaceuticals, Inc.
    Inventors: Keelung Hong, Hao-Wen Kao, Yi-Yu Lin
  • Publication number: 20220246509
    Abstract: A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. The first RDL includes a first dielectric layer disposed over the die and the first molding, and a first interconnect structure surrounded by the first dielectric layer and electrically connected to the die. The interposer is electrically connected to the die through the first interconnect structure. The first via extends through and within the second molding and is adjacent to the interposer. The second RDL includes a second dielectric layer disposed over the interposer and the second molding, and a second interconnect structure surrounded by the second dielectric layer and electrically connected to the via and the interposer.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 4, 2022
    Inventors: CHIN-HER CHIEN, PO-HSIANG HUANG, CHENG-HUNG YEH, TAI-YU WANG, MING-KE TSAI, YAO-HSIEN TSAI, KAI-YUN LIN, CHIN-YUAN HUANG, KAI-MING LIU, FONG-YUAN CHANG, CHIN-CHOU LIU, YI-KAN CHENG
  • Patent number: 11404113
    Abstract: A memory device includes a first program line and a second program line. A first portion of the first program line is formed in a first conductive layer, and a second portion of the first program line is formed in a second conductive layer above the first conductive layer. A first portion of the second program line is formed in the first conductive layer. A second portion of the second program line is formed in the second conductive layer. A third portion of the second program line is formed in a third conductive layer above the second conductive layer. The first portion and the second portion of the first program line have sizes that are different from each other, and the first portion, the second portion and the third portion of the second program line have sizes that are different from each other.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Hsin Nien, Wei-Chang Zhao, Chih-Yu Lin, Hidehiro Fujiwara, Yen-Huei Chen, Ru-Yu Wang
  • Publication number: 20220239230
    Abstract: An isolated conversion apparatus with magnetic bias balance control includes an isolated converter, a controller, and a magnetic bias balance circuit. The isolated converter includes a transformer, and a primary side of the transformer includes a primary-side winding and at least one switch bridge arm. The controller is coupled to the at least one switch bridge arm, and provides a pulse width modulation (PWM) signal group to control the at least one switch bridge arm. The magnetic bias balance circuit is coupled to two ends of the primary-side winding and the controller, and provides a compensation voltage to the controller according to an average voltage of a winding voltage across the two ends of the primary-side winding. The controller adjusts a duty cycle of the PWM signal group according to the compensation voltage to correct the magnetic bias.
    Type: Application
    Filed: January 6, 2022
    Publication date: July 28, 2022
    Inventors: Chih-Hsien LI, Yi-Ping HSIEH, Hung-Chieh LIN, Hung-Yu HUANG, Ciao-Yin PAN
  • Publication number: 20220238749
    Abstract: The present disclosure provides a contact structure and an electronic device having the same. The contact structure includes: a substrate; a copper layer disposed on the substrate; an adhesion promotion layer disposed on the copper layer, wherein the adhesion promotion layer forms a monomolecular adsorption layer on the surface of the copper layer; and a silver nanowire layer disposed on the adhesion promotion layer, and the adhesive force between the copper layer and the silver nanowire layer is 3B or more. In the present disclosure, by disposing the adhesion promotion layer on the copper layer, in the stacked structure of the copper layer and the silver nanowire layer, the adhesive force between the copper layer and the silver nanowire layer is increased, so as to prevent a peeling phenomenon of the copper layer occurring in the subsequent yellow-light process.
    Type: Application
    Filed: January 22, 2021
    Publication date: July 28, 2022
    Inventors: Yi-Min Jiang, Xi-Zhao Wang, Li-Wei Mu, Shan-Yu Wu, Chih-Min Chen, Chao-Hui Kuo, Wei-Chuan Chao, Chia Jui Lin
  • Patent number: 11387123
    Abstract: A method for fault detection in a fabrication facility is provided. The method includes moving a wafer carrier along a predetermined path multiple times using a transportation apparatus. The method also includes collecting data associated with an environmental condition within the wafer carrier or around the wafer carrier using a metrology tool on the predetermined path in a previous movement of the transportation apparatus. The method further includes measuring the environmental condition within the wafer carrier or around the wafer carrier using the metrology tool during the movement of the wafer carrier. In addition, the method includes issuing a warning when the measured environmental condition is outside a range of acceptable values. The range of acceptable values is derived from the data collected in the previous movement of the transportation apparatus.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Powen Huang, Yao-Yuan Shang, Kuo-Shu Tseng, Yen-Yu Chen, Chun-Chih Lin, Yi-Ming Dai
  • Patent number: 11387177
    Abstract: A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. The first RDL includes a first dielectric layer disposed over the die and the first molding, and a first interconnect structure surrounded by the first dielectric layer and electrically connected to the die. The interposer is electrically connected to the die through the first interconnect structure. The first via extends through and within the second molding and is adjacent to the interposer. The second RDL includes a second dielectric layer disposed over the interposer and the second molding, and a second interconnect structure surrounded by the second dielectric layer and electrically connected to the via and the interposer.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chin-Her Chien, Po-Hsiang Huang, Cheng-Hung Yeh, Tai-Yu Wang, Ming-Ke Tsai, Yao-Hsien Tsai, Kai-Yun Lin, Chin-Yuan Huang, Kai-Ming Liu, Fong-Yuan Chang, Chin-Chou Liu, Yi-Kan Cheng
  • Patent number: 11373878
    Abstract: A technique for semiconductor manufacturing is provided. The technique includes the operations as follows. A semiconductor structure having a first material and a second material is revived. The first material has a first incubation time to a first etching chemistry. The second material has a second incubation time to the first etching chemistry. The first incubation time is shorter than the second incubation time. A first main etch to the semiconductor structure for a first duration by the first etching chemistry is performed. The first duration is greater than the first incubation time and shorter than the second incubation time.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Han-Yu Lin, Li-Te Lin, Tze-Chung Lin, Fang-Wei Lee, Yi-Lun Chen, Jung-Hao Chang, Yi-Chen Lo, Fo-Ju Lin, Kenichi Sano, Pinyen Lin
  • Publication number: 20220115584
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.
    Type: Application
    Filed: November 3, 2020
    Publication date: April 14, 2022
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Ching-Hua Hsu, Yi-Yu Lin, Hung-Yueh Chen