Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.

Abstract: A bottom-pinned spin-orbit torque magnetic random access memory (SOT-MRAM) is provided in the present invention, including a substrate, a bottom electrode layer on the substrate, a magnetic tunnel junction (MTJ) on the bottom electrode layer, a spin-orbit torque (SOT) layer on the MTJ, a capping layer on the SOT layer, and an injection layer on the capping layer, wherein the injection layer is divided into individual first part and second part, and the first part and the second part are connected respectively with two ends of the capping layer.

Abstract: A method includes forming a pad layer. The pad layer includes a first portion over a first part of a semiconductor substrate, and a second portion over a second part of the semiconductor substrate. The first portion has a first thickness, and the second portion has a second thickness smaller than the first thickness. The semiconductor substrate is then annealed to form a first oxide layer over the first part of the semiconductor substrate, and a second oxide layer over the second part of the semiconductor substrate. The pad layer, the first oxide layer, and the second oxide layer are removed. A semiconductor layer is epitaxially grown over and contacting the first part and the second part of the semiconductor substrate.

Abstract: A laser machining device includes a pulsed laser generator, an accommodation chamber, a bandwidth broadening unit and a pulse compression unit. The pulsed laser generator is configured to emit a pulsed laser. The accommodation chamber has a gas inlet. The bandwidth broadening unit is disposed in the accommodation chamber, and is configured to broaden a frequency bandwidth of the pulsed laser to obtain a broad bandwidth pulsed laser. The pulse compression unit is disposed in the accommodation chamber. The bandwidth broadening unit and the pulse compression unit are arranged in order along a laser propagation path, and the pulse compression unit is configured to compress a pulse duration of the broad bandwidth pulsed laser.

Abstract: A circuit protection device includes a first temperature sensitive resistor, a second temperature sensitive resistor, an electrically insulating multilayer, a first and second electrode layer, and at least one external electrode. The first temperature sensitive resistor and the second temperature sensitive resistor are electrically connected in parallel, and have a first upper electrically conductive layer and a second lower electrically conductive layer, respectively. The electrically insulating multilayer includes an upper insulating layer, a middle insulating layer, and a lower insulating layer. The upper insulating layer is between the first upper electrically conductive layer and the first electrode layer. The middle layer is laminated between the first temperature sensitive resistor and the second temperature sensitive resistor. The lower insulating layer is between the second lower electrically conductive layer and the second electrode layer.

Abstract: A semiconductor device including a tungsten contact structure formed in a first dielectric layer on a substrate is provided. The tungsten contact structure contains a seam structure. A tungsten oxide layer is formed at least on a sidewall of the seam structure.

Abstract: A method of forming an opening pattern including the following steps is provided. An ultra low dielectric constant layer, a dielectric hard mask layer and a patterned metal hard mask layer are sequentially formed on a substrate. A portion of the dielectric hard mask layer is removed to form a patterned dielectric hard mask layer by using the patterned metal hard mask layer as a mask. The patterned metal hard mask layer is removed after forming the patterned dielectric hard mask layer. A portion of the ultra low dielectric constant layer is removed to form a first opening by using the patterned dielectric hard mask layer as a mask.

Abstract: A method of forming an opening pattern including the following steps is provided. An ultra low dielectric constant layer, a dielectric hard mask layer and a patterned metal hard mask layer are sequentially formed on a substrate. A portion of the dielectric hard mask layer is removed to form a patterned dielectric hard mask layer by using the patterned metal hard mask layer as a mask. The patterned metal hard mask layer is removed after forming the patterned dielectric hard mask layer. A portion of the ultra low dielectric constant layer is removed to form a first opening by using the patterned dielectric hard mask layer as a mask.

Abstract: A metal interconnection structure includes a substrate and a protective layer. The substrate includes at least a first conductive layer. The protective layer is a single-layered structure disposed on the substrate, and a quantity of oxygen (O) in an upper part of the protective layer is more than a quantity of oxygen (O) in a lower part of the protective layer. A material of the upper part of the protective layer includes silicon oxycarbide (SiCO) or silicon oxycarbonitride (SiCNO), and a material of the lower part of the protective layer includes silicon carbide (SiC) or silicon carbonitride (SiCN).

Abstract: A metal interconnection structure includes a substrate and a protective laver. The substrate includes at least a first conductive layer. The protective layer is a single-layered structure disposed on the substrate, and a quantity of oxygen (O) in an upper part of the protective layer is more than a quantity of oxygen (O) in a lower part of the protective layer. A material of the upper part of the protective layer includes silicon oxycarbide (SiCO) or silicon oxycarbonitride (SiCNO), and a material of the lower part of the protective layer includes silicon carbide (SiC) or silicon carbonitride (SiCN).

Abstract: An apparatus for fault detection and classification (FDC) specification management including a storage device and a process module. The storage device stores a specification management record and a chart profile record. The specification management record stores statistical algorithm settings of a parameter and the chart profile record stores chart frame and alarm condition information. The process module, which resides in a memory, receives a manipulation message corresponding to the specification management record, and accordingly manipulates the chart profile record.

Abstract: An apparatus for fault detection and classification (FDC) specification management including a storage device and a process module. The storage device stores a specification management record and a chart profile record. The specification management record stores statistical algorithm settings of a parameter and the chart profile record stores chart frame and alarm condition information. The process module, which resides in a memory, receives a manipulation message corresponding to the specification management record, and accordingly manipulates the chart profile record.