Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle and a top view of the first metal interconnection includes an ellipse overlapping the circle.

Abstract: A wearable device includes a frame element and a dielectric substrate. The frame element includes a first metal element, a second metal element, and a third metal element. A first gap is provided between the first metal element and the second metal element. A second gap is provided between the second metal element and the third metal element. A third gap is provided between the third metal element and the first metal element. The dielectric substrate is surrounded by the first metal element, the second metal element, and the third metal element. A first antenna element is formed by the first metal element. A second antenna element is formed by the second metal element. A third antenna element is formed by the third metal element.

Abstract: The present invention is directed to inhibitors of the interaction of menin with MLL and MLL fusion proteins, pharmaceutical compositions containing the same, and their use in the treatment of cancer and other diseases mediated by the menin-MLL interaction.

Abstract: A method for responding to a command is adapted for a storage device. The method for responding to a command includes following steps of: sequentially receiving a first command and a second command by a bridge of the storage device from a host; executing the first command and the second command to generate a status completion signal or a status error signal by the bridge; and detecting an error state of at least one of the first command and the second command to execute a response mode or an idle mode by the bridge according to the error state so as to respond to the host.

Abstract: At least some embodiments of the present disclosure relate to an electronic package structure. The electronic package structure includes an electronic structure, a wiring structure disposed over the electronic structure, a bonding element connecting the wiring structure and the electronic structure, and a reinforcement element attached to the wiring structure. An elevation difference between a highest point and a lowest point of a surface of the wiring structure facing the electronic structure is less than a height of the bonding element.

Abstract: A substrate processing apparatus comprises a chamber member that defines an interior volume that has an aspect ratio. The chamber member comprises a pair of laterally opposing inlet walls and a loading port. Each of the pair of laterally opposing inlet walls has an inlet port configured to receive output from a remote plasma source. The loading port is arranged between the pair of inlet walls, configured to allow passage of a substrate into the interior volume.

Abstract: Disclosed is an absorbent body comprising: 1) a water permeable topsheet; 2) a water impermeable backsheet; 3) an absorbent core disposed between the topsheet and the backsheet; and 4) a composite isolation sheet bonded to the wearer facing side of the topsheet. The composite isolation sheet comprises: a) a pair of inner cuffs having a pair of side edges which are elasticized in the longitudinal direction; b) a front portion or a back portion; and c) a longitudinal elastic element disposed on the front portion or the back portion. The longitudinal elastic element extends substantially in the longitudinal direction.

Abstract: Disclosed is an absorbent body for an absorbent article comprising 1) a water permeable topsheet; 2) a water impermeable backsheet; 3) an absorbent core disposed between the topsheet and the backsheet; and 4) a composite isolation sheet bonded to the wearer facing side of the topsheet.

Abstract: A 3D IC package is provided. The 3D IC package includes: a first IC die comprising a first substrate at a back side of the first IC die; a second IC die stacked at the back side of the first IC die and facing the first substrate; a TSV through the first substrate and electrically connecting the first IC die and the second IC die, the TSV having a TSV cell including a TSV cell boundary surrounding the TSV; and a protection module fabricated in the first substrate, wherein the protection module is electrically connected to the TSV, and the protection module is within the TSV cell.

Abstract: A method includes forming a dummy gate over a semiconductor fin; forming a source/drain epitaxial structure over the semiconductor fin and adjacent to the dummy gate; depositing an interlayer dielectric (ILD) layer to cover the source/drain epitaxial structure; replacing the dummy gate with a gate structure; forming a dielectric structure to cut the gate structure, wherein a portion of the dielectric structure is embedded in the ILD layer; recessing the portion of the dielectric structure embedded in the ILD layer; after recessing the portion of the dielectric structure, removing a portion of the ILD layer over the source/drain epitaxial structure; and forming a source/drain contact in the ILD layer and in contact with the portion of the dielectric structure.

Abstract: Technology is disclosed herein for a memory system that compensates for different programming speeds in two sets of memory cells when reading those two sets of memory cells. The memory system programs a group of the memory cells to one or more data states. In one aspect, the memory cells are not verified during programming. The group has a first set of memory cells that program at a first speed and a second set of memory cells that program at a second speed. The memory system reads the first set of the memory cells with a first set of read parameters and reads the second set of the memory cells with a second set of read parameters. The first set of read parameters are different from the second set of read parameters to compensate for the different programming speeds.

Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.

Abstract: The present disclosure relates to utilizing a buffer management system to efficiently manage and deallocate memory buffers utilized by multiple processing roles on computer hardware devices. For example, the buffer management system utilizes distributed decentralized memory buffer monitoring in connection with augmented buffer pointers to deallocate memory buffers accurately and efficiently. In this manner, the buffer management system provides an efficient approach for multiple processing roles to consume source data stored in a memory buffer and to deallocate the buffer only after all roles have finished using it.

Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

Abstract: Embodiments of the present disclosure include systems and methods for providing a scalable controller for managing data storages. A system includes a non-volatile memory controller comprising a set of data queues and a set of administrative queues. The system also includes a set of physical storages communicatively coupled to the non-volatile memory controller. A set of logical storages are created from the set of physical storages. A primary non-volatile memory controller is created from the non-volatile memory controller. The primary non-volatile memory controller comprising an administrative queue in the set of administrative queues, a first subset of the set of data queues, and a first subset of the set of logical storages. An extended non-volatile memory controller is created from the non-volatile memory controller. The extended non-volatile memory controller comprising a second subset of the set of data queues and a second subset of the set of logical storages.

Abstract: Techniques are described with respect to a system, method, and computer product for enhancement of socialization between one or more individuals wearing personal protective equipment. An associated method includes identifying a plurality of social communications between one or more individuals wearing personal protective equipment (PPE) and assigning an identifier to a participant associated with at least one of the social communications. The method further includes analyzing content of the at least one social communication and generating an augmented reality (AR) based representation of the content for presentation on an augmented reality device associated with the user, the augmented reality device presenting the content for visualization replacing PPE based at least in-part on the identifier.

Abstract: A method is provided and includes several operations: arranging multiple channels extending in a first direction; arranging, in accordance with multiple weights of multiple macros, a first portion of the macro closer to a centroid of a core region of an integrated circuit than a second portion of the macros; and arranging the macros on opposite sides of the channels. The macros have multiple pins coupled to the channels interposed between the macros.

Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.