Patents by Inventor Yi-Yuan Chen

Yi-Yuan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240139337
    Abstract: The present disclosure relates to a method for treating a cancer and/or cancer metastasis in a subject comprising administering to the subject irinotecan loaded in a mesoporous silica nanoparticle. The present disclosure also provides a conjugate comprising an agent loaded in a mesoporous silica nanoparticle (MSN) defining at least one pore and having at least one functional group on a sidewall of the at least one pore.
    Type: Application
    Filed: November 2, 2022
    Publication date: May 2, 2024
    Inventors: Cheng-Hsun WU, SI-HAN WU, YI-PING CHEN, RONG-LIN ZHANG, CHUNG-YUAN MOU, Yu-Tse LEE
  • Publication number: 20240126633
    Abstract: A method for responding to a command is adapted for a storage device. The method for responding to a command includes following steps of: sequentially receiving a first command and a second command by a bridge of the storage device from a host; executing the first command and the second command to generate a status completion signal or a status error signal by the bridge; and detecting an error state of at least one of the first command and the second command to execute a response mode or an idle mode by the bridge according to the error state so as to respond to the host.
    Type: Application
    Filed: August 14, 2023
    Publication date: April 18, 2024
    Inventors: Yi Cheng TSAI, Sung-Kao LIU, Cheng-Yuan HSIAO, Po-Hao CHEN
  • Patent number: 11961808
    Abstract: At least some embodiments of the present disclosure relate to an electronic package structure. The electronic package structure includes an electronic structure, a wiring structure disposed over the electronic structure, a bonding element connecting the wiring structure and the electronic structure, and a reinforcement element attached to the wiring structure. An elevation difference between a highest point and a lowest point of a surface of the wiring structure facing the electronic structure is less than a height of the bonding element.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: April 16, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Jen Wang, Po-Jen Cheng, Fu-Yuan Chen, Yi-Hsin Cheng
  • Publication number: 20240120203
    Abstract: A method includes forming a dummy gate over a semiconductor fin; forming a source/drain epitaxial structure over the semiconductor fin and adjacent to the dummy gate; depositing an interlayer dielectric (ILD) layer to cover the source/drain epitaxial structure; replacing the dummy gate with a gate structure; forming a dielectric structure to cut the gate structure, wherein a portion of the dielectric structure is embedded in the ILD layer; recessing the portion of the dielectric structure embedded in the ILD layer; after recessing the portion of the dielectric structure, removing a portion of the ILD layer over the source/drain epitaxial structure; and forming a source/drain contact in the ILD layer and in contact with the portion of the dielectric structure.
    Type: Application
    Filed: March 8, 2023
    Publication date: April 11, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Chih HSIUNG, Yun-Hua CHEN, Bing-Sian WU, Yi-Hsuan CHIU, Yu-Wei CHANG, Wen-Kuo HSIEH, Chih-Yuan TING, Huan-Just LIN
  • Publication number: 20240113113
    Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Chih-Chang Hung, Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Yi-Hsuan Hsiao, I-Wei Yang
  • Publication number: 20240105619
    Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 28, 2024
    Inventors: Fong-Yuan Chang, Noor Mohamed Ettuveettil, Po-Hsiang Huang, Sen-Bor Jan, Ming-Fa Chen, Chin-Chou Liu, Yi-Kan Cheng
  • Patent number: 11942543
    Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chou Lin, Yi-Cheng Chiu, Karthick Murukesan, Yi-Min Chen, Shiuan-Jeng Lin, Wen-Chih Chiang, Chen-Chien Chang, Chih-Yuan Chan, Kuo-Ming Wu, Chun-Lin Tsai
  • Publication number: 20240096701
    Abstract: A device includes: a stack of semiconductor nanostructures; a gate structure wrapping around the semiconductor nanostructures, the gate structure extending in a first direction; a source/drain region abutting the gate structure and the stack in a second direction transverse the first direction; a contact structure on the source/drain region; a backside conductive trace under the stack, the backside conductive trace extending in the second direction; a first through via that extends vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure that abuts the first through via in the second direction.
    Type: Application
    Filed: May 17, 2023
    Publication date: March 21, 2024
    Inventors: Chun-Yuan CHEN, Huan-Chieh SU, Ching-Wei TSAI, Shang-Wen CHANG, Yi-Hsun CHIU, Chih-Hao WANG
  • Patent number: 11923302
    Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fong-Yuan Chang, Noor Mohamed Ettuveettil, Po-Hsiang Huang, Sen-Bor Jan, Ming-Fa Chen, Chin-Chou Liu, Yi-Kan Cheng
  • Publication number: 20240073563
    Abstract: The present disclosure provides a time delay integration (TDI) sensor using a rolling shutter. The TDI sensor includes multiple pixel columns. Each pixel column includes multiple pixels arranged in an along-track direction, wherein two adjacent pixels or two adjacent pixel groups in every pixel column have a separation space therebetween. The separation space is equal to a pixel height multiplied by a time ratio of a line time difference of the rolling shutter and a frame period, or equal to a summation of at least one pixel height and a multiplication of the pixel height by the time ratio of the line time difference and the frame period. The TDI sensor further records defect pixels of a pixel array such that in integrating pixel data to integrators, the pixel data associated with the defect pixels is not integrated into corresponding integrators.
    Type: Application
    Filed: November 7, 2023
    Publication date: February 29, 2024
    Inventors: Ren-Chieh LIU, Chao-Chi LEE, Yi-Yuan CHEN, En-Feng HSU
  • Patent number: 11849236
    Abstract: The present disclosure provides a time delay integration (TDI) sensor using a rolling shutter. The TDI sensor includes multiple pixel columns. Each pixel column includes multiple pixels arranged in an along-track direction, wherein two adjacent pixels or two adjacent pixel groups in every pixel column have a separation space therebetween. The separation space is equal to a pixel height multiplied by a time ratio of a line time difference of the rolling shutter and a frame period, or equal to a summation of at least one pixel height and a multiplication of the pixel height by the time ratio of the line time difference and the frame period. The TDI sensor further records defect pixels of a pixel array such that in integrating pixel data to integrators, the pixel data associated with the defect pixels is not integrated into corresponding integrators.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: December 19, 2023
    Assignees: PIXART IMAGING INC., TAIWAN SPACE AGENCY
    Inventors: Ren-Chieh Liu, Chao-Chi Lee, Yi-Yuan Chen, En-Feng Hsu
  • Patent number: 11797906
    Abstract: State estimation and sensor fusion switching methods for autonomous vehicles thereof are provided. The autonomous vehicle includes at least one sensor, at least one actuator and a processor, and is configured to transfer and transport an object. In the method, a task instruction for moving the object and data required for executing the task instruction are received. The task instruction is divided into a plurality of work stages according to respective mapping locations, and each of the work stages is mapped to one of a transport state and an execution state, so as to establish a semantic hierarchy. A current location of the autonomous vehicle is detected by using the sensor and mapped to one of the work stages in the semantic hierarchy, so as to estimate a current state of the autonomous vehicle.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: October 24, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Xin-Lan Liao, Kun-Hsien Lin, Lih-Guong Jang, Wei-Liang Wu, Yi-Yuan Chen
  • Publication number: 20230202679
    Abstract: A container device of a UAV is provided. The container device is configured to receive a cargo and be connected to a UAV. The container device includes an outer housing, an inner housing, and a power supply. The outer housing is connected to the UAV. The inner housing is detachably connected to the outer housing, and configured to receive the cargo. The power supply is disposed in the inner housing. When the outer housing is connected to the UAV and the inner housing is connected to the outer housing, the power supply is electrically connected to a battery of the UAV. A transport system of a UAV is also provided.
    Type: Application
    Filed: December 27, 2021
    Publication date: June 29, 2023
    Inventors: Ming-Hsuan HO, Hon-Yue CHOU, Yi-Yuan CHEN
  • Publication number: 20230123405
    Abstract: The present disclosure provides a time delay integration (TDI) sensor using a rolling shutter. The TDI sensor includes multiple pixel columns. Each pixel column includes multiple pixels arranged in an along-track direction, wherein two adjacent pixels or two adjacent pixel groups in every pixel column have a separation space therebetween. The separation space is equal to a pixel height multiplied by a time ratio of a line time difference of the rolling shutter and a frame period, or equal to a summation of at least one pixel height and a multiplication of the pixel height by the time ratio of the line time difference and the frame period. The TDI sensor further records defect pixels of a pixel array such that in integrating pixel data to integrators, the pixel data associated with the defect pixels is not integrated into corresponding integrators.
    Type: Application
    Filed: June 27, 2022
    Publication date: April 20, 2023
    Inventors: Ren-Chieh LIU, Chao-Chi LEE, Yi-Yuan CHEN, En-Feng HSU
  • Patent number: 11631062
    Abstract: A voucher verification auxiliary method is provided, including: when a user device is approaching a voucher verification auxiliary device, generating an encryption key for the user device to encrypt voucher data with the encryption key to generate first encrypted data; reading and decrypting the first encrypted data to obtain the voucher data; encrypting the voucher data to generate and transmit second encrypted data to a verification center; decrypting the second encrypted data to obtain the voucher data, generating a verification result after verifying the voucher data, encrypting the verification result to become third encrypted data, and transmitting the third encrypted data back to the voucher verification auxiliary device; decrypting the third encrypted data to obtain the verification result; transmitting the verification result to a voucher receiving terminal. A voucher verification auxiliary device and a voucher verification auxiliary system are also provided.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: April 18, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yi-Yuan Chen, Kun-Hsien Lin, Yi-Chang Wang, Yao-Tai Tseng
  • Publication number: 20220387756
    Abstract: A urinary catheter conveying device includes a sleeve member, a conveying assembly and a controller. The sleeve member is for sleeving onto a glans of a penis and has a guiding hole to be registered with an external urethral orifice of the glans. The conveying assembly includes a casing removably mounted to the sleeve member, and a conveying mechanism for advancing the urinary catheter to the guiding hole such that the urinary catheter is inserted into the external urethral orifice. The controller controls the conveying mechanism to advance the urinary catheter to the guiding hole. A urinary catheterization system and a method of using the urinary catheterization system are also disclosed.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 8, 2022
    Inventors: Chung-Cheng Wang, Yung-Ping Wang, Yi-Yuan Chen, Chia-Ming Hsu, Ming-Chien Chiu, Chia-Ch Lin
  • Patent number: 11361178
    Abstract: A communication system and method thereof are provided, which includes: providing a first mask, a second mask, a user device having a screen and a display device having a light code module and a panel, wherein the first mask and the second mask are positioned at different positions of the panel, respectively; providing a light code signal to the panel by the light code module, and providing a first mask signal and a second mask signal by the first mask and the second mask, respectively; and capturing the light code signal plus the first mask signal or the second mask signal from the panel by the user device to obtain a first code according to the combination of the light code signal and the first mask signal or obtain a second code according to the combination of the light code signal and the second mask signal.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: June 14, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: Kun-Hsein Lin, Lih-Guong Jang, Yi-Yuan Chen
  • Publication number: 20220147727
    Abstract: A communication system and method thereof are provided, which includes: providing a first mask, a second mask, a user device having a screen and a display device having a light code module and a panel, wherein the first mask and the second mask are positioned at different positions of the panel, respectively; providing a light code signal to the panel by the light code module, and providing a first mask signal and a second mask signal by the first mask and the second mask, respectively; and capturing the light code signal plus the first mask signal or the second mask signal from the panel by the user device to obtain a first code according to the combination of the light code signal and the first mask signal or obtain a second code according to the combination of the light code signal and the second mask signal.
    Type: Application
    Filed: December 22, 2020
    Publication date: May 12, 2022
    Inventors: Kun-Hsein Lin, Lih-Guong Jang, Yi-Yuan Chen
  • Patent number: D1017381
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: March 12, 2024
    Assignee: QBIC TECHNOLOGY CO., LTD.
    Inventors: Yi-Hsin Chen, Wei-Yuan Cheng, Ren-Yin Wu Ji
  • Patent number: D1019349
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: March 26, 2024
    Assignee: QBIC TECHNOLOGY CO., LTD.
    Inventors: Yi-Hsin Chen, Wei-Yuan Cheng, Ren-Yin Wu Ji