Patents by Inventor Yi-Yueh Hsu

Yi-Yueh Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240130246
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.
    Type: Application
    Filed: December 25, 2023
    Publication date: April 18, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Ching-Hua Hsu, Yi-Yu Lin, Hung-Yueh Chen
  • Patent number: 11957061
    Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Yi-Yu Lin, Ching-Hua Hsu, Hung-Yueh Chen
  • Patent number: 11925035
    Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.
    Type: Grant
    Filed: October 26, 2022
    Date of Patent: March 5, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Kai Hsu, Hui-Lin Wang, Ching-Hua Hsu, Yi-Yu Lin, Ju-Chun Fan, Hung-Yueh Chen
  • Publication number: 20230261147
    Abstract: A light-emitting diode display includes a substrate, multiple light-emitting diodes, an under fill, and an encapsulant. The light-emitting diodes are disposed on the substrate. The under fill is disposed between the substrate and the light-emitting diodes. The under fill includes multiple portions, and the portions are respectively located between two adjacent ones of the light-emitting diodes. A height of at least one of the portions is different from the heights of the other portions. The encapsulant is disposed on the under fill and the light-emitting diodes.
    Type: Application
    Filed: December 30, 2022
    Publication date: August 17, 2023
    Inventors: Yi-Yueh HSU, Kuan-Hsun CHEN, Hsin-Ni YANG, Wei-Lung LIAU
  • Publication number: 20230187417
    Abstract: A display panel includes a substrate, light-emitting diodes, and a cured opaque encapsulant layer. The light-emitting diodes are disposed on a first surface of the substrate. The cured opaque encapsulant layer is disposed on the first surface and a side surface of the substrate, and surrounds the light emitting diodes. A second surface of the cured opaque encapsulant layer facing away from the substrate is a rough surface.
    Type: Application
    Filed: April 1, 2022
    Publication date: June 15, 2023
    Applicant: Au Optronics Corporation
    Inventors: Fu-Wei Chan, Kuan-Hsun Chen, Yi-Yueh Hsu
  • Publication number: 20230097567
    Abstract: Provided is a manufacturing method of an active device substrate including the following steps. A blind hole is formed in a substrate. A first conductive pattern and an active device are formed on a first surface of the substrate, where the first conductive pattern overlaps the blind hole. After the first conductive pattern and the active device are formed, an etching process is executed on the substrate to form a through hole penetrating the substrate at the position of the blind hole. A conductive material is filled into the through hole to form a conductive hole. The conductive hole is electrically connected to the first conductive pattern. A second conductive pattern is formed on a second surface of the substrate, where the second conductive pattern is electrically connected to the first conductive pattern through the conductive hole.
    Type: Application
    Filed: November 4, 2021
    Publication date: March 30, 2023
    Applicant: Au Optronics Corporation
    Inventors: Yi-Yueh Hsu, Kuan-Hsun Chen