Patents by Inventor Yi-Yun Li

Yi-Yun Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11975741
    Abstract: An automated guided vehicle control system includes a commodity database, a historical shopping information acquisition module, a purchase-item prediction module, an automated guided vehicle database, an automated guided vehicle dispatch demand assessment module and an automated guided vehicle dispatch module. The historical shopping information acquisition module is utilized to retrieve the historical shopping information related to the customer, further to locate the instant predicted commodity to be purchased, and thereby to dispatch the suitable automated guided vehicle to the waiting area of the customer. Further, the historical shopping information is evaluated to provide the commodity type options for the customer to select, to locate the commodity type to be purchased, and thereby to organize the automated navigation path for the automated guided vehicle to travel along to reach the assigned commodity display area.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: May 7, 2024
    Assignee: TECO ELECTRIC & MACHINERY CO., LTD.
    Inventors: Yi-Ting Li, Cheng-Yun Chung
  • Publication number: 20230114216
    Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a fin structure on a substrate. The fin structure includes a plurality of first nanostructures and a plurality of second nanostructures alternately stacked. A dummy gate is formed along sidewalls and a top surface of the fin structure. A portion of the fin structure exposed by the dummy gate is recessed to form a first recess. An epitaxial source/drain region is formed in the first recess. Dopant atoms within the epitaxial source/drain region are driven into the plurality of second nanostructures. The dummy gate and the plurality of first nanostructures are removed. A replacement gate is formed wrapping around the plurality of second nanostructures.
    Type: Application
    Filed: May 13, 2022
    Publication date: April 13, 2023
    Inventors: Yi-Yun Li, Tsai-Yu Huang, Li-Ting Wang, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11563110
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate and forming an isolation structure over the substrate. In addition, the fin structure is protruded from the isolation structure. The method further includes trimming the fin structure to a first width and forming a Ge-containing material covering the fin structure. The method further includes annealing the fin structure and the Ge-containing material to form a modified fin structure. The method also includes trimming the modified fin structure to a second width.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: January 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Yun Li, Tsai-Yu Huang, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20210242334
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate and forming an isolation structure over the substrate. In addition, the fin structure is protruded from the isolation structure. The method further includes trimming the fin structure to a first width and forming a Ge-containing material covering the fin structure. The method further includes annealing the fin structure and the Ge-containing material to form a modified fin structure. The method also includes trimming the modified fin structure to a second width.
    Type: Application
    Filed: January 19, 2021
    Publication date: August 5, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Yun LI, Tsai-Yu HUANG, Huicheng CHANG, Yee-Chia YEO
  • Patent number: 10879371
    Abstract: Embodiments described in this disclosure relate to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In some examples, after an interfacial layer and a gate dielectric layer are deposited, a rapid anneal process, such as laser anneal or flash lamp anneal process, is performed in a controlled ambient nitrogen-containing environment to form a nitrided portion in the gate dielectric layer. The nitrided portion passivates the defects at the surface of the gate dielectric layer and can serve as a barrier to prevent etchant chemistry and defects/dopants from the subsequent gate stack layers from affecting or diffusing through the gate dielectric layer. Particularly, the rapid anneal process is performed on a millisecond scale to confine nitrogen atoms in the gate dielectric layer without diffusing into the underlying interfacial dielectric and/or any neighboring structure such as fin.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Yun Li, Huicheng Chang, Che-Hao Chang, Hung-Yao Chen, Cheng-Po Chau, Xiong-Fei Yu, Terry Huang
  • Publication number: 20190378913
    Abstract: Embodiments described in this disclosure relate to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In some examples, after an interfacial layer and a gate dielectric layer are deposited, a rapid anneal process, such as laser anneal or flash lamp anneal process, is performed in a controlled ambient nitrogen-containing environment to form a nitrided portion in the gate dielectric layer. The nitrided portion passivates the defects at the surface of the gate dielectric layer and can serve as a barrier to prevent etchant chemistry and defects/dopants from the subsequent gate stack layers from affecting or diffusing through the gate dielectric layer. Particularly, the rapid anneal process is performed on a millisecond scale to confine nitrogen atoms in the gate dielectric layer without diffusing into the underlying interfacial dielectric and/or any neighboring structure such as fin.
    Type: Application
    Filed: June 12, 2018
    Publication date: December 12, 2019
    Inventors: Yi-Yun Li, Huicheng Chang, Che-Hao Chang, Hung-Yao Chen, Cheng-Po Chau, Xiong-Fei Yu, Terry Huang