Abstract: A method for optimizing a manual assembly layout, executed by a processing device, including: analyzing the assembly operation and the operating time corresponding to the assembly operation of each of the assemblers based on the operating information of one or more assemblers; generating a plurality of candidate solutions based on the assembly operations, the operating time, and a plurality of condition parameters; selecting at least one of the candidate solutions to be the optimal solution based on the workload balance information of each of the candidate solutions.

Abstract: Provided is a power transistor device including a substrate, a first electrode, and a second electrode. The substrate has an active region and a terminal region. The terminal region surrounds the active region. The substrate includes a first trench and a second trench. The first trench is disposed within the active region and adjacent to the terminal region. The second trench is disposed within the terminal region and adjacent to the active region. The first electrode and the second electrode are respectively disposed in the first trench and the second trench. The first electrode and the second electrode both are electrically floating.

Abstract: Provided is a power transistor device including a substrate, a first electrode, and a second electrode. The substrate has an active region and a terminal region. The terminal region surrounds the active region. The substrate includes a first trench and a second trench. The first trench is disposed within the active region and adjacent to the terminal region. The second trench is disposed within the terminal region and adjacent to the active region. The first electrode and the second electrode are respectively disposed in the first trench and the second trench. The first electrode and the second electrode both are electrically floating.

Abstract: A semiconductor apparatus including a substrate, an electrostatic discharge protection device, a resistor device, and a first metal layer is provided. The substrate defines a pad area and includes a first area and a second area. The first area has a recess, the second area is disposed in the recess, and the pad area is partially overlapped with the first area and the second area. The electrostatic discharge protection device is disposed in the first area of the substrate. The resistor device is disposed in the second area of the substrate. The first metal layer is disposed above and electrically connected to the electrostatic discharge protection device and the resistor device.

Abstract: Provided is a trench gate MOSFET including a substrate of a first conductivity type, an epitaxial layer of the first conductivity type, a first conductive layer of a second conductivity type, a second conductive layer and an interlayer insulating layer. The epitaxial layer is disposed on the substrate and has at least one trench therein. The first conductive layer is disposed in the lower portion of the trench and in physical contact with the epitaxial layer. The second conductive layer is disposed in the upper portion of the trench. The interlayer insulating layer is disposed between the first conductive layer and the second conductive layer.

Abstract: Provided is a trench gate MOSFET including a substrate of a first conductivity type, an epitaxial layer of the first conductivity type, a first conductive layer of a second conductivity type, a second conductive layer and an interlayer insulating layer. The epitaxial layer is disposed on the substrate and has at least one trench therein. The first conductive layer is disposed in the lower portion of the trench and in physical contact with the epitaxial layer. The second conductive layer is disposed in the upper portion of the trench. The interlayer insulating layer is disposed between the first conductive layer and the second conductive layer.

Abstract: A semiconductor apparatus including a substrate, an electrostatic discharge protection device, a resistor device, and a first metal layer is provided. The substrate defines a pad area and includes a first area and a second area. The first area has a recess, the second area is disposed in the recess, and the pad area is partially overlapped with the first area and the second area. The electrostatic discharge protection device is disposed in the first area of the substrate. The resistor device is disposed in the second area of the substrate. The first metal layer is disposed above and electrically connected to the electrostatic discharge protection device and the resistor device.

Abstract: A semiconductor structure including a substrate, a first dielectric layer, a first conductive layer, a positioning part, two spacers, and a second conductive layer is provided. The substrate has a first trench. The first dielectric layer is disposed on a surface of the first trench. The first conductive layer is filled in the first trench and located on the first dielectric layer. The positioning part is disposed on the substrate and has a first opening. The first opening exposes the first trench. The spacers are disposed on two sidewalls of the first opening and expose the first conductive layer. The second conductive layer is filled in the first opening and electrically connected to the first conductive layer. The semiconductor structure can prevent the generation of leakage current while maintaining a high breakdown voltage.

Abstract: A semiconductor structure including a substrate, a first dielectric layer, a first conductive layer, a positioning part, two spacers, and a second conductive layer is provided. The substrate has a first trench. The first dielectric layer is disposed on a surface of the first trench. The first conductive layer is filled in the first trench and located on the first dielectric layer. The positioning part is disposed on the substrate and has a first opening. The first opening exposes the first trench. The spacers are disposed on two sidewalls of the first opening and expose the first conductive layer. The second conductive layer is filled in the first opening and electrically connected to the first conductive layer. The semiconductor structure can prevent the generation of leakage current while maintaining a high breakdown voltage.

Abstract: A power semiconductor device of stripe cell geometry including a substrate, a plurality of striped power semiconductor units, and a guard ring structure is provided. The substrate has an active area and a termination area surrounding the active area defined thereon. The striped semiconductor unit includes a striped gate conductive structure. The striped semiconductor units are located in the active area. The guard ring structure is located in the termination area and includes at least a ring-shaped conductive structure surrounding the striped power semiconductor units. The ring-shaped conductive structure and the striped gate conductive structures are formed on the same conductive layer, and at least one of the striped gate conductive structures is separated from the nearby ring-shaped conductive structure and electrically connected to the nearby ring-shaped conductive structure through the gate metal pad.

Abstract: A power semiconductor device of stripe cell geometry including a substrate, a plurality of striped power semiconductor units, and a guard ring structure is provided. The substrate has an active area and a termination area surrounding the active area defined thereon. The striped semiconductor unit includes a striped gate conductive structure. The striped semiconductor units are located in the active area. The guard ring structure is located in the termination area and includes at least a ring-shaped conductive structure surrounding the striped power semiconductor units. The ring-shaped conductive structure and the striped gate conductive structures are formed on the same conductive layer, and at least one of the striped gate conductive structures is separated from the nearby ring-shaped conductive structure and electrically connected to the nearby ring-shaped conductive structure through the gate metal pad.

Abstract: A trenched power semiconductor device on a lightly doped substrate is provided. The device has a base, a plurality of trenches including at least a gate trench, a plurality of first heavily doping regions, a body region, a source doped region, a contact window, a second heavily doped region, and a metal layer. The trenches are formed in the base. The first heavily doped regions are beneath the trenches respectively and spaced from the bottom of the respective trench with a lightly doped region. The body region encircles the trenches and is away from the first heavily doped region with a predetermined distance. The source doped region is in an upper portion of the body region. The contact window is adjacent to the edge of the base. The second heavily doped region is below the contact window filled by the metal layer for electrically connecting the second heavily doped region.

Abstract: A closed cell trenched power semiconductor structure is provided. The closed cell trenched power semiconductor structure has a substrate and cells. The cells are arranged on the substrate in an array. Every cell has a body and a trenched gate. The trenched gate surrounds the body. A side wall of the trenched gate facing body has a concave.

Abstract: A trenched power semiconductor device on a lightly doped substrate is provided. Firstly, a plurality of trenches including at least a gate trench and a contact window are formed on the lightly doped substrate. Then, at least two trench-bottom heavily doped regions are formed at the bottoms of the trenches. These trench-bottom heavily doped regions are then expanded to connect with each other by using thermal diffusion process so as to form a conductive path. Afterward, the gate structure and the well are formed above the trench-bottom heavily doped regions, and then a conductive structure is formed in the contact window to electrically connect the trench-bottom heavily doped regions to an electrode.

Abstract: A closed cell trenched power semiconductor structure is provided. The closed cell trenched power semiconductor structure has a substrate and cells. The cells are arranged on the substrate in an array. Every cell has a body and a trenched gate. The trenched gate surrounds the body. A side wall of the trenched gate facing body has a concave.

Abstract: A fabrication method of a trenched power MOSFET is provided. A pattern layer having a first opening is formed on a substrate. A portion of the substrate is removed, using the pattern layer as a mask, to form a trench in the substrate. A width of the trench is expanded. A gate oxide layer is formed on a surface of the trench. A portion of the gate oxide layer on a bottom of the trench is removed, using the pattern layer as a mask, to form a second opening in the gate oxide layer. The width of the expanded trench is greater than that of the second opening. A thick oxide layer is formed in the second opening. Heavily doped regions are formed beside the thick oxide layer. A gate is formed in the trench. A body layer surrounding the trench is formed. Sources are formed beside the trench.

Abstract: A trenched power semiconductor device on a lightly doped substrate is provided. The device has a base, a plurality of trenches including at least a gate trench, a plurality of first heavily doping regions, a body region, a source doped region, a contact window, a second heavily doped region, and a metal layer. The trenches are formed in the base. The first heavily doped regions are beneath the trenches respectively and spaced from the bottom of the respective trench with a lightly doped region. The body region encircles the trenches and is away from the first heavily doped region with a predetermined distance. The source doped region is in an upper portion of the body region. The contact window is adjacent to the edge of the base. The second heavily doped region is below the contact window filled by the metal layer for electrically connecting the second heavily doped region.

Abstract: A trenched power semiconductor device on a lightly doped substrate is provided. Firstly, a plurality of trenches including at least a gate trench and a contact window are formed on the lightly doped substrate. Then, at least two trench-bottom heavily doped regions are formed at the bottoms of the trenches. These trench-bottom heavily doped regions are then expanded to connect with each other by using thermal diffusion process so as to form a conductive path. Afterward, the gate structure and the well are formed above the trench-bottom heavily doped regions, and then a conductive structure is formed in the contact window to electrically connect the trench-bottom heavily doped regions to an electrode.

Abstract: A fabrication method of a trenched power MOSFET is provided. A pattern layer having a first opening is formed on a substrate. A portion of the substrate is removed, using the pattern layer as a mask, to form a trench in the substrate. A width of the trench is expanded. A gate oxide layer is formed on a surface of the trench. A portion of the gate oxide layer on a bottom of the trench is removed, using the pattern layer as a mask, to form a second opening in the gate oxide layer. The width of the expanded trench is greater than that of the second opening. A thick oxide layer is formed in the second opening. Heavily doped regions are formed beside the thick oxide layer. A gate is formed in the trench. A body layer surrounding the trench is formed. Sources are formed beside the trench.

Abstract: An organic thin film transistor including a substrate, a gate, a gate insulator, an adhesive layer, a metal nano-particle layer and an organic semiconductor layer is provided. The gate is disposed on the substrate. The gate insulator is disposed on the gate and the substrate. The adhesive layer is disposed on the gate insulator. Besides, the adhesive layer has a hydrophobic surface above the gate and a first hydrophilic surface and a second hydrophilic surface on two sides of the hydrophobic surface. A surface of the metal nano-particle layer is modified by a hydrophilic group, and the metal nano-particle layer is disposed on the first and the second hydrophilic surfaces of the adhesive layer as a source and a drain, respectively. The organic semiconductor layer is disposed on the hydrophobic surface of the adhesive layer and on the metal nano-particle layer.