Abstract: Provided is a microfluidic chip. The microfluidic chip includes a first substrate and a second substrate disposed opposite to each other, a microfluidic channel formed between the first substrate and the second substrate and configured to accommodate at least one droplet, drive electrodes arranged in an array and sensing electrodes disposed on a side of the first substrate. Each sensing electrode includes at least one first branch electrode and at least one second branch electrode. The first branch electrode extends along a first direction, and the second branch electrode extends along a second direction. Different drive voltage signals are applied to adjacent drive electrodes to drive the droplet to move. Detection signals are applied to the sensing electrodes, and a position of the droplet is determined according to a change in capacitance between one sensing electrode and an electrode corresponding thereto when the droplet flows by.

Abstract: A driving circuit includes a first signal-input terminal, a second signal-input terminal, a third signal-input terminal, a fourth signal-input terminal, a signal-output terminal, and a voltage-boosting unit including a first module, a second module, a third module, and a first capacitor. The first module transmits the signal at the third signal-input terminal to a first terminal of the first capacitor during a first time period, and blocks signal transmission during a second time period. During the first time period and the second time period, the second module transmits the signal at the third signal-input terminal to the third module to allow the signal at the fourth signal-input terminal to be transmitted to a second terminal of the first capacitor. During a third time period, the second module and the third module both block signal transmission. The first terminal of the first capacitor is connected to the signal-output terminal for output.

Abstract: A driving circuit includes a first signal-input terminal, a second signal-input terminal, a third signal-input terminal, a fourth signal-input terminal, a signal-output terminal, and a voltage-boosting unit including a first module, a second module, a third module, and a first capacitor. The first module transmits the signal at the third signal-input terminal to a first terminal of the first capacitor during a first time period, and blocks signal transmission during a second time period. During the first time period and the second time period, the second module transmits the signal at the third signal-input terminal to the third module to allow the signal at the fourth signal-input terminal to be transmitted to a second terminal of the first capacitor. During a third time period, the second module and the third module both block signal transmission. The first terminal of the first capacitor is connected to the signal-output terminal for output.

Abstract: A gate shift register unit comprises an activation signal terminal, a deactivation signal terminal, a reset signal terminal, a first level signal terminal, a second level signal terminal, a first control terminal, a first clock signal terminal, a second clock signal terminal, an output terminal, a first node, a second node, a first node control unit, a second node control unit, a reset unit, and an output unit. The first node control unit is connected to the first control terminal, the activation signal terminal, the first level signal terminal, the second level signal terminal, the deactivation signal terminal, the first node, and the second node, and configured to transfer a signal at the first level signal terminal or the second level signal terminal to the first node under a control of potential signals at the activation signal terminal, the deactivation signal terminal, the first control terminal, and the second node.

Abstract: An array substrate, an electronic paper display panel and a driving method are provided. The array substrate includes at least two display areas provided with a plurality of data signal lines, and a peripheral circuit area provided with a plurality of signal leads, a plurality of switch modules and surrounding the at least two display areas. Each one data signal line is electrically connected to one signal lead through one switch module. Further, the array substrate includes at least two control signal lines provided in the peripheral circuit area. All control terminals of the switch modules corresponding to all the data signal lines in single one display area are electrically connected to the same one control signal line, and the control terminals of the switch modules corresponding to the data signal lines in different display areas are electrically connected to different control signal lines.

Abstract: An electronic paper display panel, including a first and second substrate; an electrophoresis layer arranged between the first and second substrates, the electrophoresis layer including black electrophoretic particle, white electrophoretic particle and at least one color electrophoretic particle; a first electrode layer arranged at a side of the first substrate facing the second substrate including multiple first electrodes; a second electrode layer arranged at a side of the second substrate facing the first substrate including multiple second electrodes; and a drive circuit; multiple pixel areas correspond multiple second electrodes; each first electrode includes a first sub-electrode and a second sub-electrode placed in same pixel area, which are insulated from each other, correspond to one second electrode and are connected with drive circuit, the first sub-electrode receives voltage signal different from voltage signal the second sub-electrode receives; the first electrode is common electrode and the seco

Abstract: An electronic paper display panel, including a first and second substrate; an electrophoresis layer arranged between the first and second substrates, the electrophoresis layer including black electrophoretic particle, white electrophoretic particle and at least one color electrophoretic particle; a first electrode layer arranged at a side of the first substrate facing the second substrate including multiple first electrodes; a second electrode layer arranged at a side of the second substrate facing the first substrate including multiple second electrodes; and a drive circuit; multiple pixel areas correspond multiple second electrodes; each first electrode includes a first sub-electrode and a second sub-electrode placed in same pixel area, which are insulated from each other, correspond to one second electrode and are connected with drive circuit, the first sub-electrode receives voltage signal different from voltage signal the second sub-electrode receives; the first electrode is common electrode and the seco

Abstract: A gate shift register unit comprises an activation signal terminal, a deactivation signal terminal, a reset signal terminal, a first level signal terminal, a second level signal terminal, a first control terminal, a first clock signal terminal, a second clock signal terminal, an output terminal, a first node, a second node, a first node control unit, a second node control unit, a reset unit, and an output unit. The first node control unit is connected to the first control terminal, the activation signal terminal, the first level signal terminal, the second level signal terminal, the deactivation signal terminal, the first node, and the second node, and configured to transfer a signal at the first level signal terminal or the second level signal terminal to the first node under a control of potential signals at the activation signal terminal, the deactivation signal terminal, the first control terminal, and the second node.

Abstract: An array substrate, an electronic paper display panel and a driving method are provided. The array substrate includes at least two display areas provided with a plurality of data signal lines, and a peripheral circuit area provided with a plurality of signal leads, a plurality of switch modules and surrounding the at least two display areas. Each one data signal line is electrically connected to one signal lead through one switch module. Further, the array substrate includes at least two control signal lines provided in the peripheral circuit area. All control terminals of the switch modules corresponding to all the data signal lines in single one display area are electrically connected to the same one control signal line, and the control terminals of the switch modules corresponding to the data signal lines in different display areas are electrically connected to different control signal lines.