Abstract: A system for processing images may comprise a pixel configuration circuitry enabled to set for each pixel in a pixel array one of a plurality of integration times and one of a plurality of signal gains. A column analog-to-digital converter may be enabled to generate a corresponding digital data for a pixel in the pixel array, and digital processing circuitry may be enabled to interpolate output data from the corresponding digital data for pixels grouped into pixel groups, wherein the pixel group comprises a target pixel and neighboring pixels in a same color plane.

Abstract: Circuits, methods, and apparatus are described that provide calibration of column-parallel analog-to-digital converters (ADCs) in image processing contexts only once per frame (or less frequently) to reduce column-wise noise. For example, the column ADCs are calibrated during an inter-frame time interval, like a vertical blanking interval. In some embodiments, calibration data for the column ADCs for a calibration period is stored at the digital block for use in processing row data from the column ADCs. In other embodiments, calibration data for the column ADCs for the calibration period is stored at column ADCs in a local memory for local correction of the pixel data prior to being read out to the digital block for processing. In certain embodiments, techniques, such as differential ADC architectures, are used to mitigate row-wise noise in context of the frame-wise calibration.

Abstract: Circuits, methods, and apparatus that provide differential-input, single-slope, column-parallel analog-to-digital converter (ADC) architectures for use in high-resolution CMOS image sensors (CIS) are described. A column ADC is coupled with a column of a pixel array and configured to convert a pixel signal level to a corresponding digital output value according to a ramp generator output. Each pixel is configured to output a pixel reset level and a pixel signal level at different operating stages, and the ramp generator output includes a ramp reset level and a ramp signal level at the same or different at different operating stages. The pixel and ramp outputs are used to differentially drive a comparator stage of the column ADC, for example, to reduce power supply noise.

Abstract: Aspects of the invention provide dynamic range extension for CMOS image sensors for mobile applications. An embodiment of the invention may comprise setting for each pixel in a pixel array one of a plurality of integration times and one of a plurality of signal gains, wherein the settings may be used to generate corresponding digital data for each pixel in the pixel array. The corresponding digital data for adjacent pixels for the same color plane may then be grouped into a superpixel, where each pixel has associated with it a different combination of integration time and signal gain.

Abstract: Aspects of the invention provide a continuous ramp generator design and its calibration for CMOS image sensors using single-ramp ADCs. An embodiment of the invention comprises controlling a coarse gain, integer gain, and fine gain of the analog-to-digital converter. Gain of the analog-to-digital converter may be calibrated by tuning the integer gain based on reference voltages converted to equivalent digital values.

Abstract: Various embodiments of the present invention include enabling, during a calibration phase, a counter to count one less than a number of clock periods associated with a determined offset. The counted number of the clock periods is stored in calibration memory. In a conversion phase, inverted outputs are loaded from the calibration memory to the counter, where the counter is enabled to count the clock periods to determine a digital equivalent value of an analog signal amplitude.

Abstract: Various embodiments of the invention include enabling, during a calibration phase, a counter to count one less than a number of clock periods associated with a determined offset. The counted number of the clock periods is stored in calibration memory. In a conversion phase, inverted outputs are loaded from the calibration memory to the counter, where the counter is enabled to count the clock periods to determine a digital equivalent value of an analog signal amplitude.

Abstract: Various embodiments of the present invention include enabling, during a calibration phase, a counter to count one less than a number of clock periods associated with a determined offset. The counted number of the clock periods is stored in calibration memory. In a conversion phase, inverted outputs are loaded from the calibration memory to the counter, where the counter is enabled to count the clock periods to determine a digital equivalent value of an analog signal amplitude.

Abstract: An active pixel sensor (APS) that includes circuitry to eliminate artifacts in digital images. The APS includes a comparator for comparing a signal level from a pixel to an adjusted saturation voltage to determine if the pixel is saturated. If the pixel is saturated, the signal output from the pixel is replaced with an analog voltage having a maximum value corresponding to a brightest pixel in the image.

Abstract: A system for processing images may comprise a pixel configuration circuitry enabled to set for each pixel in a pixel array one of a plurality of integration times and one of a plurality of signal gains. A column analog-to-digital converter may be enabled to generate a corresponding digital data for a pixel in the pixel array, and digital processing circuitry may be enabled to interpolate output data from the corresponding digital data for pixels grouped into pixel groups, wherein the pixel group comprises a target pixel and neighboring pixels in a same color plane.

Abstract: Aspects of the invention provide a continuous ramp generator design and its calibration for CMOS image sensors using single-ramp ADCs. An embodiment of the invention comprises controlling a coarse gain, integer gain, and fine gain of the analog-to-digital converter. Gain of the analog-to-digital converter may be calibrated by tuning the integer gain based on reference voltages converted to equivalent digital values.

Abstract: Aspects of the invention may include receiving a first input signal and a second input signal via respective first and second input transistors. A biasing signal, generated by a cascode bias generator, tracks the first input signal, where the biasing signal has a fixed offset with respect to the first input signal. The biasing signal may be applied to the first and second cascode transistors that may be cascoded to the first and second input transistors, respectively.

Abstract: Various embodiments of the invention include enabling, during a calibration phase, a counter to count one less than a number of clock periods associated with a determined offset. The counted number of the clock periods is stored in calibration memory. In a conversion phase, inverted outputs are loaded from the calibration memory to the counter, where the counter is enabled to count the clock periods to determine a digital equivalent value of an analog signal amplitude.

Abstract: Aspects of the invention provide dynamic range extension for CMOS image sensors for mobile applications. An embodiment of the invention may comprise setting for each pixel in a pixel array one of a plurality of integration times and one of a plurality of signal gains, wherein the settings may be used to generate corresponding digital data for each pixel in the pixel array. The corresponding digital data for adjacent pixels for the same color plane may then be grouped into a superpixel, where each pixel has associated with it a different combination of integration time and signal gain.

Abstract: An image processing system includes a pixel array including a plurality of regular pixel columns and at least one test pixel column, a plurality of column analog-to-digital converters (ADCs) configured to correspond to the regular pixel columns and convert analog input signals into digital signals, and a switching block configured to provide output signals of the regular pixel columns to input ends of the corresponding column ADCs in a normal mode, and provide in common an output signal of the test pixel column to the input ends of the column ADCs in a test mode, wherein the test pixel column generates signals having a minute voltage different from one row to another row.

Abstract: An active pixel sensor (APS) that includes circuitry to eliminate artifacts in digital images. The APS includes a comparator for comparing a signal level from a pixel to an adjusted saturation voltage to determine if the pixel is saturated. If the pixel is saturated, the signal output from the pixel is replaced with an analog voltage having a maximum value corresponding to a brightest pixel in the image.

Abstract: Circuits, methods, and apparatus that provide differential-input, single-slope, column-parallel analog-to-digital converter (ADC) architectures for use in high-resolution CMOS image sensors (CIS) are described. A column ADC is coupled with a column of a pixel array and configured to convert a pixel signal level to a corresponding digital output value according to a ramp generator output. Each pixel is configured to output a pixel reset level and a pixel signal level at different operating stages, and the ramp generator output includes a ramp reset level and a ramp signal level at the same or different at different operating stages. The pixel and ramp outputs are used to differentially drive a comparator stage of the column ADC, for example, to reduce power supply noise.

Abstract: Circuits, methods, and apparatus are described that provide calibration of column-parallel analog-to-digital converters (ADCs) in image processing contexts only once per frame (or less frequently) to reduce column-wise noise. For example, the column ADCs are calibrated during an inter-frame time interval, like a vertical blanking interval. In some embodiments, calibration data for the column ADCs for a calibration period is stored at the digital block for use in processing row data from the column ADCs. In other embodiments, calibration data for the column ADCs for the calibration period is stored at column ADCs in a local memory for local correction of the pixel data prior to being read out to the digital block for processing. In certain embodiments, techniques, such as differential ADC architectures, are used to mitigate row-wise noise in context of the frame-wise calibration.

Abstract: An active pixel sensor (APS) that includes circuitry to eliminate artifacts in digital images. The APS includes a comparator for comparing a signal level from a pixel to an adjusted saturation voltage to determine if the pixel is saturated. If the pixel is saturated, the signal output from the pixel is replaced with an analog voltage having a maximum value corresponding to a brightest pixel in the image.

Abstract: An active pixel sensor (APS) that includes circuitry to eliminate artifacts in digital images. The APS includes a comparator for comparing a signal level from a pixel to an adjusted saturation voltage to determine if the pixel is saturated. If the pixel is saturated, the signal output from the pixel is replaced with an analog voltage having a maximum value corresponding to a brightest pixel in the image.