Abstract: A pixel circuit of the present invention includes a thin-film transistor, a first scan line, a second scan line, and a data line. The first scan line is arranged along a first direction. The first scan line is electrically connected to the thin-film transistor. The second scan line is arranged along a second direction. The second scan line is electrically connected to the first scan line. The second direction is perpendicular to the first direction. The data line is arranged along the second direction. The data line is electrically connected to the thin-film transistor. The pixel circuit also includes an auxiliary scan line. The auxiliary scan line is arranged along the second direction. Two ends of the auxiliary scan line are electrically connected to the second scan line.

Abstract: A splicing display panel is provided. The splicing display panel includes at least two spliced first display modules and at least one second display module. There is a seam between two adjacent first display modules. A portion of the first display module corresponding to a bezel area is provided with an accommodating slot. The accommodating slot of one of the first display modules is spliced with the accommodating slot of another one of the first display modules to form an accommodating cavity.

Abstract: A display panel is provided. The display panel includes a plurality of pixels, a first main data line, a first sub data line, and a first connecting line. The first main data line is electrically connected to pixels arranged in at least two columns. The first sub data line and the first main data line are separated by M columns of pixels, and the first sub data line is electrically connected to pixels arranged in at least two other columns. The first connecting line connects the first main data line and the first sub data line.

Abstract: A splicing display panel and a splicing display device are provided. The splicing display panel includes at least two spliced first display modules and at least one second display module. There is a seam between two adjacent first display modules. A portion of the first display module corresponding to a bezel area is provided with an accommodating slot. The accommodating slot of one of the first display modules is spliced with the accommodating slot of another one of the first display modules to form an accommodating cavity. The at least one second display module is arranged in the accommodating cavity, and the second display module covers the seam.

Abstract: A pixel array, a display panel, and a display device are provided. The pixel array includes a first pixel electrode, a first data line, and a second data line. The first pixel electrode includes a first side and a second side opposite to the first side. The first data line is electrically connected to the first pixel electrode. The first data line is adjacent to the first side of the first pixel electrode and extends to the second side. The second data line is adjacent to the first data line. At least a portion of the second data line is disposed between the second side and the first data line. The first data line and the second data line are respectively configured to transmit signals with opposite polarities.

Abstract: A pixel circuit of the present invention includes a thin-film transistor, a first scan line, a second scan line, and a data line. The first scan line is arranged along a first direction. The first scan line is electrically connected to the thin-film transistor. The second scan line is arranged along a second direction. The second scan line is electrically connected to the first scan line. The second direction is perpendicular to the first direction. The data line is arranged along the second direction. The data line is electrically connected to the thin-film transistor. The pixel circuit also includes an auxiliary scan line. The auxiliary scan line is arranged along the second direction. Two ends of the auxiliary scan line are electrically connected to the second scan line.

Abstract: A splicing display panel and a splicing display device are provided. The splicing display panel includes at least two spliced first display modules and at least one second display module. There is a seam between two adjacent first display modules. A portion of the first display module corresponding to a bezel area is provided with an accommodating slot. The accommodating slot of one of the first display modules is spliced with the accommodating slot of another one of the first display modules to form an accommodating cavity. The at least one second display module is arranged in the accommodating cavity, and the second display module covers the seam.

Abstract: A display panel is provided, including a power line, light-emitting lamp groups, partition channel wirings, driving chips, and a grounding signal wiring. The driving chips, the light-emitting lamp groups, and the partition channel wirings are disposed between the power line and the grouping signal wiring spaced apart. The driving chips are connected to the grounding signal wiring. The light-emitting lamp groups are connected to the power line. The partition channel wirings are connected to the light-emitting lamp groups. The power line, the grounding signal wiring, and the partition channel wirings are disposed in a same layer.

Abstract: A pixel array, a display panel, and a display device are provided. The pixel array includes a first pixel electrode, a first data line, and a second data line. The first pixel electrode includes a first side and a second side opposite to the first side. The first data line is electrically connected to the first pixel electrode. The first data line is adjacent to the first side of the first pixel electrode and extends to the second side. The second data line is adjacent to the first data line. At least a portion of the second data line is disposed between the second side and the first data line. The first data line and the second data line are respectively configured to transmit signals with opposite polarities.

Abstract: A display panel is provided. The display panel includes a plurality of pixels, a first main data line, a first sub data line, and a first connecting line. The first main data line is electrically connected to pixels arranged in at least two columns. The first sub data line and the first main data line are separated by M columns of pixels, and the first sub data line is electrically connected to pixels arranged in at least two other columns. The first connecting line connects the first main data line and the first sub data line.