Patents by Inventor Yichen Fang

Yichen Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240392089
    Abstract: A cellulose acetate foam having a density of less than 0.20 g/cm3 and an average foam cell size of less than 200 micrometers is disclosed. A foamable composition, a method for foaming a foam and articles including, prepared or formed from the foam are also described.
    Type: Application
    Filed: September 1, 2022
    Publication date: November 28, 2024
    Applicant: Eastman Chemical Company
    Inventors: BETHANY MICHELLE ADEN, GAURAV AMARPURI, GOLIATH BENIAH, STEPHANIE KAY CLENDENNEN, MICHAEL EUGENE DONELSON, Yichen Fang, THILANGA PRABHASH LIYANA ARACHCHI, STEVEN THOMAS PERRI, WAYNE KEN SHIH
  • Publication number: 20240327621
    Abstract: The present application discloses melt processable cellulose ester compositions comprising a cellulose ester, at least one alkaline additive, and at least one neutralizing agent. Plasticizers can be optionally used in the compositions. The present application also discloses processes for preparing the compositions and articles that can be made from the compositions. The compositions show improved degradation properties.
    Type: Application
    Filed: October 7, 2022
    Publication date: October 3, 2024
    Applicant: Eastman Chemical Company
    Inventors: STEPHANIE KAY CLENDENNEN, YICHEN FANG
  • Publication number: 20240130139
    Abstract: A ferroelectric memory includes at least one storage cell. Each storage cell includes a transistor, a first ferroelectric capacitor, and at least one voltage divider capacitor. The transistor includes a gate electrode, a source electrode, and a drain electrode. One electrode of the first ferroelectric capacitor is connected to the gate electrode. The other electrode of the first ferroelectric capacitor is connected to a word line. One electrode of each voltage divider capacitor in the at least one voltage divider capacitor is connected to the gate electrode, and the other electrode of each voltage divider capacitor in the at least one voltage divider capacitor is connected to the source electrode.
    Type: Application
    Filed: July 26, 2023
    Publication date: April 18, 2024
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Zhaozhao Hou, Sitong Bu, Yichen Fang, Yu Zhang, JEFFREY JUNHAO XU
  • Publication number: 20230276636
    Abstract: Example ferroelectric memories and storage devices are described One example ferroelectric memory includes at least one bit cell. A bit cell in the at least one bit cell includes a plurality of ferroelectric capacitors and a first transistor. The first transistor includes a first gate, a first channel, a first source, and a first drain. The first source and the first drain are located at two ends of the first channel. One electrode of each of the plurality of ferroelectric capacitors is formed on the first gate.
    Type: Application
    Filed: May 3, 2023
    Publication date: August 31, 2023
    Inventors: Jeffrey Junhao XU, Weiliang JING, Sitong BU, Yichen FANG, Ying WU, Zhaozhao HOU, Wanliang TAN, Heng ZHANG, Yu ZHANG
  • Patent number: 9431620
    Abstract: The present invention discloses an organic resistive random access memory and a preparation method thereof. The memory uses silicon as a substrate, and has a MIM capacitor structure having a vertical memory unit, where the MIM structure has a top electrode of Al, a bottom electrode of ITO, and an middle functional layer of parylene, wherein, a parylene layer as the functional layer is formed by performing deposition multiple times, where the deposition of Al2O3 is performed once by ALD between each two deposition of parylene. A critical region which is in favor of forming a conductive channel could be formed by controlling the deposition area of Al2O3, and further control the electrical characteristics of the memory. Through the present invention, the cycle-to-cycle and device-to-device uniformity could be effectively improved, without changing the basic structure of the memory.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: August 30, 2016
    Assignee: Peking University
    Inventors: Yimao Cai, Yefan Liu, Wenliang Bai, Zongwei Wang, Yichen Fang, Ru Huang
  • Publication number: 20160240778
    Abstract: Disclosed are a multi-value nonvolatile organic resistive random access memory and a method for preparing the same. The resistive random access memory comprises a top electrode, a bottom electrode and a middle functional layer located between the top electrode and the bottom electrode, the middle functional layer is at least two layers of parylene. The method comprises the steps of: growing material for the bottom electrode using physical vapor deposition method on a substrate; growing sequentially multiple layers of parylene on the bottom electrode by polymer chemical vapor deposition; defining the via for leading out the bottom electrode by lithography and etching; growing material for the top electrode on the parylene materials by using physical vapor deposition process, defining the top electrode material by lithography and lift-off, and leading out the bottom electrode.
    Type: Application
    Filed: March 31, 2014
    Publication date: August 18, 2016
    Inventors: Yimao Cai, Yefan Liu, Yichen Fang, Zongwei Wang, Qiang Li, Muxi Yu, Yue Pan, Ru Huang
  • Publication number: 20160110644
    Abstract: The present invention discloses a time correlation learning neuron circuit based on a resistive memristor and an implementation method thereof. The present invention utilizes switching characteristics of the resistive memristor. When two terminals of the resistive memristor are selected synchronously by two excitation signals, the voltage drop between these two terminals will change the resistance value of memristor, thereby achieving the on-off of a synapse connection and achieving the correction of the two excitation signals. Meanwhile the device also has a memory characteristic. Also, the previous excitation signal can be repeated. That is, the purpose of learning is achieved. Since the resistive memristor has a simple structure and a high degree of integration, it can achieve large-scale physical synapse connection in order to achieve more complex learning and even logic functions. The present invention has a good application prospect in a neuron cell computation.
    Type: Application
    Filed: September 30, 2013
    Publication date: April 21, 2016
    Inventors: Ru Huang, Yaokai Zhang, Yimao Cai, Fan Yang, Yue Pan, Zongwei Wang, Yichen Fang
  • Patent number: 9281476
    Abstract: Embodiments of the present invention disclose a resistive memory and a method for fabricating the same. The resistive memory comprises a bottom electrode, a resistive layer and a top electrode. The resistive layer is located over the bottom electrode. The top electrode is located over the resistive layer. A conductive protrusion is provided on the bottom electrode. The conductive protrusion is embedded in the resistive layer, and has a top width smaller than a bottom width. Embodiments of the present invention further disclose a method for fabricating a resistive memory. According to the resistive memory and the method for fabricating the same provided by the embodiments of the present invention, by means of providing the conductive protrusion on the bottom electrode, a “lightning rod” effect may be occurred so that an electric field in the resistive layer is intensively distributed near the conductive protrusion.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: March 8, 2016
    Assignee: Peking University
    Inventors: Yimao Cai, Shihui Yin, Ru Huang, Yichen Fang
  • Publication number: 20160049604
    Abstract: The present invention discloses an organic resistive random access memory and a preparation method thereof. The memory uses silicon as a substrate, and has a MIM capacitor structure having a vertical memory unit, where the MIM structure has a top electrode of Al, a bottom electrode of ITO, and an middle functional layer of parylene, wherein, a parylene layer as the functional layer is formed by performing deposition multiple times, where the deposition of Al2O3 is performed once by ALD between each two deposition of parylene. A critical region which is in favor of forming a conductive channel could be formed by controlling the deposition area of Al2O3, and further control the electrical characteristics of the memory. Through the present invention, the cycle-to-cycle and device-to-device uniformity could be effectively improved, without changing the basic structure of the memory.
    Type: Application
    Filed: September 30, 2013
    Publication date: February 18, 2016
    Inventors: Yimao Cai, Yefan Liu, Wenliang Bai, Zongwei Wang, Yichen Fang, Ru Huang
  • Publication number: 20150144861
    Abstract: Embodiments of the present invention disclose a resistive memory and a method for fabricating the same. The resistive memory comprises a bottom electrode, a resistive layer and a top electrode. The resistive layer is located over the bottom electrode. The top electrode is located over the resistive layer. A conductive protrusion is provided on the bottom electrode. The conductive protrusion is embedded in the resistive layer, and has a top width smaller than a bottom width. Embodiments of the present invention further disclose a method for fabricating a resistive memory. According to the resistive memory and the method for fabricating the same provided by the embodiments of the present invention, by means of providing the conductive protrusion on the bottom electrode, a “lightning rod” effect may be occurred so that an electric field in the resistive layer is intensively distributed near the conductive protrusion.
    Type: Application
    Filed: July 8, 2013
    Publication date: May 28, 2015
    Inventors: Yimao Cai, Shihui Yin, Ru Huang, Yichen Fang