Abstract: A semiconductor structure includes a fin structure over a substrate, a source/drain feature in the fin structure, a gate stack across the fin structure, a contact plug over the source/drain feature, a first dielectric layer over the contact plug, and a second dielectric layer over the first dielectric layer, and a via through the second dielectric layer and the first dielectric layer and on the contact plug. A width of the via varies along a vertical direction, and the via has a minimum width at a first level that is higher than a top surface of the first dielectric layer.

Abstract: A semiconductor structure includes a contact plug on a source/drain region of a transistor, and a via on the contact plug. The via includes a lower portion and an upper portion over the lower portion, the lower portion of the via tapers upward, and the upper portion of the via tapers downward. The semiconductor structure further includes a metal line on the via.

Abstract: An exemplary method according to the present disclosure includes forming a first dielectric layer over a first conductive feature, forming a second dielectric layer over the first dielectric layer, forming a patterned mask over the second dielectric layer, performing a first etching process to form a trench extending through the first dielectric layer and the second dielectric layer to expose a top surface of the first conductive feature, where etchant of the first etching process modifies a portion of the first dielectric layer exposed by the trench, performing a second etching process to remove the patterned mask and the modified portion of the first dielectric layer, where etchant of the second etching process further reacts with a part of a remaining portion of the first dielectric layer to cause a volume expansion of the remaining portion of the first dielectric layer, and forming a second conductive feature in the trench.

Abstract: One aspect of the present disclosure pertains to a semiconductor device. The semiconductor device includes a source/drain (S/D) contact over an S/D feature; a gate structure over a channel region, where the channel region is adjacent the S/D feature; a first interlayer dielectric (ILD) layer over the gate structure and surrounding the S/D contact; an etch stop layer over the first ILD layer and the S/D contact, where the etch stop layer includes a first portion and a second portion, and the second portion is different from the first portion in chemical composition; a second ILD layer over the etch stop layer; and a gate via over the gate structure, where the gate via is surrounded by the second portion of the etch stop layer.

Abstract: A device comprises a source/drain contact over a source/drain region of a transistor, an etch stop layer above the source/drain contact, an interlayer dielectric (ILD) layer above the etch stop layer, and a source/drain via extending through the ILD layer and the etch stop layer to the source/drain contact. The etch stop layer has an oxidized region in contact with the source/drain via and separated from the source/drain contact.

Abstract: Conductive contacts, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a first interlayer dielectric (ILD) layer over a transistor structure; a first contact extending through the first ILD layer, the first contact being electrically coupled with a first source/drain region of the transistor structure, a top surface of the first contact being convex, and the top surface of the first contact being disposed below a top surface of the first ILD layer; a second ILD layer over the first ILD layer and the first contact; and a second contact extending through the second ILD layer, the second contact being electrically coupled with the first contact.

Abstract: A method includes removing a dummy gate stack to form a first trench between gate spacers, forming a replacement gate stack in the first trench, recessing the replacement gate stack to form a second trench between the gate spacers, selectively depositing a conductive capping layer in the second trench, forming a dielectric hard mask in the second trench and over the conductive capping layer, and etching the dielectric hard mask using an etching gas to form an opening in the dielectric hard mask. The replacement gate stack is revealed to the opening. The conductive capping layer is more resistant to the etching gas than the replacement gate stack. The method further comprises forming a gate contact plug over and contacting the conductive capping layer.

Abstract: Embodiments provide a dielectric inter block disposed in a metallic region of a conductive line or source/drain contact. A first and second conductive structure over the metallic region may extend into the metallic region on either side of the inter block. The inter block can prevent etchant or cleaning solution from contacting an interface between the first conductive structure and the metallic region.

Abstract: Embodiments provide a dielectric inter block disposed in a metallic region of a conductive line or source/drain contact. A first and second conductive structure over the metallic region may extend into the metallic region on either side of the inter block. The inter block can prevent etchant or cleaning solution from contacting an interface between the first conductive structure and the metallic region.

Abstract: A method for detecting the presence and the correct or incorrect placement of target objects in a container or carrier divides the container space into areas where the states of placement of the target objects in the container can be recognized, to generate N number of sub-areas, N is a positive integer. An artificial intelligence model is obtained by training the same according to training images of objects, the training images being images of the N sub-areas. The images are input into the artificial intelligence model and the states of placement are determined. The disclosure also provides an electronic device and a non-transitory storage medium.

Abstract: A semiconductor device includes a channel structure, a first gate structure straddling the channel structure, and an epitaxial structure. The epitaxial structure is adjacent to the first gate structure and is coupled to an end of the channel structure. The semiconductor device further includes a first contact structure disposed over and in contact with the epitaxial structure and a nitride-based conformal layer extending at least over the first contact structure. The semiconductor device further includes an oxide-based layer disposed over the nitride-based conformal layer. A portion of the nitride-based conformal layer, disposed over the first contact structure, has a dip that is filled with a first portion of the oxide-based layer.

Abstract: A Chinese herbal medicine extract, a method for preparing the same, and a use of the same are disclosed. The Chinese herbal medicine extract includes an active ingredient, which contains any one of or any combination of agarwood, Chinese honeylocust fruit, Chinese honeylocust spine, cinnamon leaf, and camphor leaf. Medication based on the Chinese herbal medicine extract is useful in treating coronavirus-related symptoms or diseases.

Abstract: An information handling system keyboard illuminates key values in each of plural keycaps with a backlight located below the plural keys and directed upward through the plural keys and having illumination that adjusts color temperature under management of a controller. A light sensor detects ambient light color temperature and communicates the ambient light color temperature to the controller, which executes instructions in non-transitory memory to adjust the backlight color illumination based on the detected ambient light color temperature to increase color contrast of backlight illumination relative to ambient light and thereby better highlight the key values on the keycap upper surfaces.

Abstract: An information handling system keyboard illuminates key values in each of plural keycaps with a backlight located below the plural keys and directed upward through the plural keys and having illumination that adjusts color temperature under management of a controller. A light sensor detects ambient light color temperature and communicates the ambient light color temperature to the controller, which executes instructions in non-transitory memory to adjust the backlight color illumination based on the detected ambient light color temperature to increase color contrast of backlight illumination relative to ambient light and thereby better highlight the key values on the keycap upper surfaces.

Abstract: The invention discloses an astaxanthin (AST) nanoemulsion and its manufacturing method. The manufacturing method comprising steps of: adding an AST material into a peanut oil and mixing them uniformly to obtain an AST oil; adding 0.25-1.5 (w/w) % of a surfactant into the AST oil and mixing them uniformly to obtain a mixed solution; and adding water into the mixed solution to obtain an AST emulsion precursor; and shaking the AST emulsion precursor to obtain the AST nanoemulsion.

Abstract: A semiconductor device includes a channel structure, a first gate structure straddling the channel structure, and an epitaxial structure. The epitaxial structure is adjacent to the first gate structure and is coupled to an end of the channel structure. The semiconductor device further includes a first contact structure disposed over and in contact with the epitaxial structure and a nitride-based conformal layer extending at least over the first contact structure. The semiconductor device further includes an oxide-based layer disposed over the nitride-based conformal layer. A portion of the nitride-based conformal layer, disposed over the first contact structure, has a dip that is filled with a first portion of the oxide-based layer.

Abstract: A semiconductor device includes source/drain contacts, a gate structure, a gate dielectric cap, an etch stop layer, and a gate contact. The source/drain contacts are over a substrate. The gate structure is laterally between the source/drain contacts. The gate dielectric cap is over the gate structure and in contact with the source/drain contacts. The etch stop layer is over the source/drain contacts and the gate dielectric cap. The etch stop layer has an oxidized region directly above the gate dielectric cap. The gate contact extends through the etch stop layer and the gate dielectric cap to the gate structure. The gate contact and the oxidized region of the etch stop layer form an interface perpendicular to the substrate.

Abstract: Embodiments include a contact structure and method of forming the same where the contact structure is deliberately positioned near the end of a metallic line. An opening is formed in an insulating structure positioned over the metallic line and then the opening is extended into the metallic line by an etching process. In the etching process, the line end forces etchant to concentrate back away from the line end, causing lateral etching of the extended opening. A subsequent contact is formed in the opening and enlarged opening.

Abstract: A method includes removing a dummy gate stack to form a first trench between gate spacers, forming a replacement gate stack in the first trench, recessing the replacement gate stack to form a second trench between the gate spacers, selectively depositing a conductive capping layer in the second trench, forming a dielectric hard mask in the second trench and over the conductive capping layer, and etching the dielectric hard mask using an etching gas to form an opening in the dielectric hard mask. The replacement gate stack is revealed to the opening. The conductive capping layer is more resistant to the etching gas than the replacement gate stack. The method further comprises forming a gate contact plug over and contacting the conductive capping layer.