Patents by Inventor Yick Yaw Darren Ho

Yick Yaw Darren Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Clock phase adjustment using clock and data recovery scheme
    Patent number: 10374785
    Abstract: Some embodiments include apparatus and methods using clock generation circuitry to generate a first clock signal and a second clock signal based on an input clock signal, the first and second clock signals having different phases, sampler circuitry to sample an input signal based on timing of the first and second clock signals and provide data information and error information associated with sampling of the input signal, a clock and data recovery unit to generate first control information based on the data information and the error information, and a phase error detection unit to generate second control information based on the data information and the error information, the clock generation circuitry to control timing of the input clock signal based on the first control information and to control timing of the first and second clock signals based on the second control information.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Yick Yaw Darren Ho, Michael W Altmann
  • CLOCK PHASE ADJUSTMENT USING CLOCK AND DATA RECOVERY SCHEME
    Publication number: 20180183633
    Abstract: Some embodiments include apparatus and methods using clock generation circuitry to generate a first clock signal and a second clock signal based on an input clock signal, the first and second clock signals having different phases, sampler circuitry to sample an input signal based on timing of the first and second clock signals and provide data information and error information associated with sampling of the input signal, a clock and data recovery unit to generate first control information based on the data information and the error information, and a phase error detection unit to generate second control information based on the data information and the error information, the clock generation circuitry to control timing of the input clock signal based on the first control information and to control timing of the first and second clock signals based on the second control information.
    Type: Application
    Filed: December 27, 2016
    Publication date: June 28, 2018
    Inventors: Yick Yaw Darren Ho, Michael W. Altmann