Abstract: One illustrative high bandwidth transimpedance amplifier includes a distributed amplifier having multiple transistors that receive a propagating input signal at respective nodes of an input signal line and drive corresponding nodes of an amplified signal line that propagates an amplified signal to an output voltage buffer. A feedback impedance couples the output voltage to a feedback node in the distributed amplifier, making the output voltage proportional to the input signal's current. An illustrative method includes: propagating an input signal current along an input signal line of a distributed amplifier, the distributed amplifier responsively propagating an amplified signal along an amplified signal line; buffering the amplified signal from a final node of the amplified signal line to produce an output voltage signal; and using the output voltage signal to draw the input signal current from a final node of the input signal line via a feedback impedance.

Abstract: Disclosed successive approximation register analog-to-digital converters (SAR ADCs) and conversion methods detect a statistical effect of meta-stability induced errors and limit the level of such errors. One illustrative integrated circuit chip includes: a SAR ADC that employs asynchronous bit cycles to convert a sequence of analog signal samples into a sequence of digital signal samples; and a detector that accelerates the asynchronous bit cycles when a meta-stability error bias exceeds a predetermined threshold. An illustrative analog-to-digital conversion method includes: converting a sequence of analog signal samples to a sequence of digital signal samples using a successive approximation register analog to digital converter (SAR ADC) with asynchronous bit cycles; deriving a meta-stability error bias from the sequence of digital signal samples; and accelerating the asynchronous bit cycles when the meta-stability error bias exceeds a predetermined threshold.

Abstract: Power supply noise reduction methods and low drop out (LDO) voltage regulators with capacitively coupled supply noise-reducing components are disclosed. One illustrative voltage regulator includes: a pass transistor having an n-type conduction channel that couples a supply voltage to an output node; an operational amplifier that derives a control signal for the pass transistor from a difference between a reference voltage and a scaled or unscaled voltage of the output node, the control signal being supplied to a gate or base of the pass transistor; a buffer that derives a ripple cancellation signal from the supply voltage; and a coupling capacitor that couples the buffer to the base or gate of the pass transistor to impose the ripple cancellation signal on the control signal.

Abstract: Power supply noise reduction methods and low drop out (LDO) voltage regulators with capacitively coupled supply noise-reducing components are disclosed. One illustrative voltage regulator includes: a pass transistor having an n-type conduction channel that couples a supply voltage to an output node; an operational amplifier that derives a control signal for the pass transistor from a difference between a reference voltage and a scaled or unscaled voltage of the output node, the control signal being supplied to a gate or base of the pass transistor; a buffer that derives a ripple cancellation signal from the supply voltage; and a coupling capacitor that couples the buffer to the base or gate of the pass transistor to impose the ripple cancellation signal on the control signal.

Abstract: The present invention is directed to communication systems and electrical circuits. According to an embodiment, the present invention provides a termination circuit that includes an inductor network. The inductor network is coupled to a termination resistor and a capacitor network, which includes a first capacitor and a second capacitor. The termination resistor, the first capacitor, and the second capacitor are adjustable, and they affect attenuation of the termination circuit. There are other embodiments as well.

Abstract: Varactors may be employed to enable enhanced performance and/or reduced power consumption of integration-based voltage comparators. One illustrative voltage comparator includes: a latch having two sense transistors to set a latch to either of two complementary states; two varactors each coupled to enable one of the two sense transistors upon reaching a turn on voltage; and a differential amplifier to charge or discharge the two varactors at a differential rate proportional to a difference in input voltages. An illustrative voltage comparison method includes: converting two input voltages into two respective currents; applying each of the two respective currents to one of two respective varactors; and deriving a latch state from the varactor voltages, the latch state indicating which of the two input voltages is greater.

Abstract: One illustrative high bandwidth transimpedance amplifier includes a distributed amplifier having multiple transistors that receive a propagating input signal at respective nodes of an input signal line and drive corresponding nodes of an amplified signal line that propagates an amplified signal to an output voltage buffer. A feedback impedance couples the output voltage to a feedback node in the distributed amplifier, making the output voltage proportional to the input signal's current. An illustrative method includes: propagating an input signal current along an input signal line of a distributed amplifier, the distributed amplifier responsively propagating an amplified signal along an amplified signal line; buffering the amplified signal from a final node of the amplified signal line to produce an output voltage signal; and using the output voltage signal to draw the input signal current from a final node of the input signal line via a feedback impedance.

Abstract: Disclosed successive approximation register analog-to-digital converters (SAR ADCs) and conversion methods detect a statistical effect of meta-stability induced errors and limit the level of such errors. One illustrative integrated circuit chip includes: a SAR ADC that employs asynchronous bit cycles to convert a sequence of analog signal samples into a sequence of digital signal samples; and a detector that accelerates the asynchronous bit cycles when a meta-stability error bias exceeds a predetermined threshold. An illustrative analog-to-digital conversion method includes: converting a sequence of analog signal samples to a sequence of digital signal samples using a successive approximation register analog to digital converter (SAR ADC) with asynchronous bit cycles; deriving a meta-stability error bias from the sequence of digital signal samples; and accelerating the asynchronous bit cycles when the meta-stability error bias exceeds a predetermined threshold.

Abstract: The present invention is directed to communication systems and electrical circuits. According to an embodiment, the present invention provides a termination circuit that includes an inductor network. The inductor network is coupled to a termination resistor and a capacitor network, which includes a first capacitor and a second capacitor. The termination resistor, the first capacitor, and the second capacitor are adjustable, and they affect attenuation of the termination circuit. There are other embodiments as well.