Patents by Inventor Yider Wu

Yider Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10297607
    Abstract: A non-volatile memory having discrete isolation structures and SONOS (Silicon Oxide Nitride Oxide Silicon) memory cells, a method of operating the same, and a method of manufacturing the same are introduced. Every isolation structure on a semiconductor substrate having an array region has a plurality of gaps so as to form discrete isolation structures and thereby implant source lines in the gaps of the semiconductor substrate. Since the source lines are not severed by the isolation structures, the required quantity of barrier pins not connected to the source line is greatly reduced, thereby reducing the space required for the barrier pins in the non-volatile memory.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 21, 2019
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventors: Takao Akaogi, Yider Wu, Yi-Hsiu Chen
  • Patent number: 8802537
    Abstract: A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The memory device is pre-cleaned to prepare a surface of the memory device for oxide formation thereon, where cleaning the memory device removes portions of the barrier oxide layer on opposite sides of the trench. The nitride layer is trimmed on opposite sides of the trench. A liner oxide layer is formed in the trench.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: August 12, 2014
    Assignee: Spansion LLC
    Inventors: Yider Wu, Unsoon Kim, Kuo-Tung Chang, Harpreet Sachar
  • Patent number: 8759894
    Abstract: A memory device is provided including a substrate. A first dielectric layer is formed over the substrate. An isolation trench is formed in a portion of the substrate and the first dielectric layer. At least two charge storage elements are formed over the first dielectric layer on opposite sides of the isolation trench. A second dielectric layer is formed over the at least two charge storage elements. A control gate layer is formed over the second dielectric layer, where the isolation trench has a width suitable for reducing cross-coupling noise of charge storage elements, and where the at least two charge storage elements have a height suitable for providing sufficient gate coupling between the at least two charge storage elements and the control gate layer.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: June 24, 2014
    Assignees: Spansion LLC, Globalfoundries Inc.
    Inventors: Yider Wu, Hiroyuki Ogawa, Unsoon Kim, Angela T. Hui
  • Publication number: 20140078832
    Abstract: A non-volatile memory having discrete isolation structures and SONOS memory cells, a method of operating the same, and a method of manufacturing the same are introduced. Every isolation structure on a semiconductor substrate having an array region has a plurality of gaps so as to form discrete isolation structures and thereby implant source lines in the gaps of the semiconductor substrate. Since the source lines are not severed by the isolation structures, the required quantity of barrier pins not connected to the source line is greatly reduced, thereby reducing the space required for the barrier pins in the non-volatile memory.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: EON SILICON SOLUTION, INC.
    Inventors: TAKAO AKAOGI, YIDER WU, YI-HSIU CHEN, HUNG-HUI LAI
  • Patent number: 8647969
    Abstract: A method of manufacturing a memory device includes forming a first dielectric layer over a substrate, forming a charge storage element over the first dielectric layer and forming an inter-gate dielectric over the charge storage element. The method also includes depositing a silicon control gate layer over the inter-gate dielectric using a reactant that contains chlorine.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: February 11, 2014
    Assignee: Spansion LLC
    Inventors: Rinji Sugino, Yider Wu, Minh Van Ngo, Jeffrey Sinclair Glick, Kuo Tung Chang
  • Publication number: 20140030860
    Abstract: A manufacturing method of tunnel oxide of NOR flash memory controls the temperature and thickness of tunnel oxide in a gate structure to prevent a channel region to change its doping concentration and range due to a high-temperature manufacturing process, so as to overcome the leakage current and improve the reliability of storing data.
    Type: Application
    Filed: July 24, 2012
    Publication date: January 30, 2014
    Inventors: YIDER WU, YI-HSIU CHEN, WEN-CHENG LEE
  • Patent number: 8598645
    Abstract: A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: December 3, 2013
    Assignees: Spansion LLC, Advanced Micro Devices, Inc.
    Inventors: Unsoon Kim, Angela T. Hui, Yider Wu, Kuo-Tung Chang, Hiroyuki Kinoshita
  • Publication number: 20130171815
    Abstract: In a manufacturing method of a flash memory structure with a stress area, a better stress effect can be achieved by controlling the manufacturing process of a tunneling oxide layer formed in a gate structure and contacted with a silicon substrate, so that an L-shaped spacer (or a first stress area) and a contact etch stop layer (or a second stress area) of each L-shaped spacer are formed between two gate structures and aligned towards each other to enhance the carrier mobility of the gate structure, so as to achieve the effects of improving a read current, obtaining the required read current by using a lower read voltage, reducing the possibility of having a stress-induced leakage current, and enhancing the data preservation of the flash memory.
    Type: Application
    Filed: December 28, 2011
    Publication date: July 4, 2013
    Inventors: YIDER WU, HUNG-WEI CHEN
  • Patent number: 8476156
    Abstract: In a manufacturing method of a flash memory structure with a stress area, a better stress effect can be achieved by controlling the manufacturing process of a tunneling oxide layer formed in a gate structure and contacted with a silicon substrate, so that an L-shaped spacer (or a first stress area) and a contact etch stop layer (or a second stress area) of each L-shaped spacer are formed between two gate structures and aligned towards each other to enhance the carrier mobility of the gate structure, so as to achieve the effects of improving a read current, obtaining the required read current by using a lower read voltage, reducing the possibility of having a stress-induced leakage current, and enhancing the data preservation of the flash memory.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: July 2, 2013
    Assignee: Eon Silicon Solution Inc.
    Inventors: Yider Wu, Hung-Wei Chen
  • Patent number: 8325518
    Abstract: A multi-level cell NOR flash memory device includes a plurality of gate lines, a plurality of source regions, a plurality of drain regions, a plurality of source lines, a plurality of bitlines, and a plurality of power lines. The bitlines each have a specific sheet resistance. A specific number of the bitlines are disposed between two adjacent ones of the power lines. Accordingly, the multi-level cell NOR flash memory device is of a high transconductance and uniformity and thereby features an enhanced conforming rate.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: December 4, 2012
    Assignee: Eon Silicon Solution Inc.
    Inventors: Sheng-Da Liu, Yider Wu
  • Publication number: 20120163077
    Abstract: A multi-level cell NOR flash memory device includes a plurality of gate lines, a plurality of source regions, a plurality of drain regions, a plurality of source lines, a plurality of bitlines, and a plurality of power lines. The bitlines each have a specific sheet resistance. A specific number of the bitlines are disposed between two adjacent ones of the power lines. Accordingly, the multi-level cell NOR flash memory device is of a high transconductance and uniformity and thereby features an enhanced conforming rate.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Applicant: EON SILICON SOLUTION INC.
    Inventors: SHENG-DA LIU, YIDER WU
  • Publication number: 20120094450
    Abstract: A manufacturing method of a multi-level cell NOR flash memory includes the steps of forming a memory cell area and a peripheral circuit area with the same depth of a shallow trench isolation structure, and the depth ranges from 2400 ? to 2700 ?; forming a non-self-aligned gate structure; performing a self-alignment source manufacturing process; and forming a common source area and a plurality of drain areas. The manufacturing method achieves a high integration density between components and provides a better thermal budget and a better dosage control to the multi-level cell NOR flash memory to improve the production yield rate.
    Type: Application
    Filed: October 19, 2010
    Publication date: April 19, 2012
    Applicant: EON SILICON SOLUTION INC.
    Inventors: Yider Wu, Sheng-Da Liu
  • Patent number: 8158519
    Abstract: In a method of manufacturing a non-volatile memory cell, a self-aligned metal silicide is used in place of a conventional tungsten metal layer to form a polysilicon gate, and the self-aligned metal silicide is used as a connection layer on the polysilicon gate. By using the self-aligned metal silicide to form the polysilicon gate, the use of masks in the etching process may be saved to thereby enable simplified manufacturing process and accordingly, reduced manufacturing cost. Meanwhile, the problem of resistance shift caused by an oxidized tungsten metal layer can be avoided.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: April 17, 2012
    Assignee: Eon Silicon Solution Inc.
    Inventors: Yi-Hsiu Chen, Yung-Chung Lee, Yider Wu
  • Patent number: 8133801
    Abstract: A method of manufacturing a memory device includes forming a first dielectric layer over a substrate, forming a charge storage element over the first dielectric layer and forming an inter-gate dielectric over the charge storage element. The method also includes depositing a silicon control gate layer over the inter-gate dielectric using a reactant that contains chlorine.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: March 13, 2012
    Assignee: Spansion LLC
    Inventors: Rinji Sugino, Yider Wu, Minh Van Ngo, Jeffrey Sinclair Glick, Kuo-Tung Chang
  • Patent number: 8093646
    Abstract: The present invention provides a flash memory device and method for making the same having a floating gate structure with a semiconductor substrate and shallow trench isolation (STI) structure formed in the substrate. A first polysilicon layer is formed over the substrate and the STI structure. The recess formed within the first polysilicon layer is over the STI structure and extends through the first polysilicon layer to the STI structure. An oxide fill is provided within the recess and is etched back. ONO (oxide-nitride-oxide) layer conformally covers the oxide fill and the first polysilicon layer. The second polysilicon layer covers the ONO layer. The oxide fill within the recess provides a minimum spacing between the second polysilicon layer and the corner of the STI regions, thereby avoiding the creation of a weak spot and reducing the risk of gate breakdown, gate leakage, and improving device reliability.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: January 10, 2012
    Assignee: Spansion LLC
    Inventors: Angela Hui, Yider Wu
  • Publication number: 20110230028
    Abstract: In a manufacturing method of a straight word line NOR flash memory array, a source line is implanted after the formation of a word line in the NOR type flash memory array is completed, and a discrete implant region is formed in the NOR type flash memory array and parallel to a component isolation structure, and each discrete implant region constitutes an electric connection with a low impedance between a source line and source contacts on the source line. With such discrete distribution, adjacent memory cells will not be short-circuited or failed even if a deviation of a mash occurs during the manufacturing process.
    Type: Application
    Filed: March 22, 2010
    Publication date: September 22, 2011
    Inventors: Yider Wu, Hung-Wei Chen
  • Patent number: 8017488
    Abstract: A manufacturing method of a NOR flash memory with phosphorous and arsenic ion implantations mainly implants both phosphorous and arsenic ions on a drain area of a transistor memory unit, and controls specific energy and dosage for the implantation to reduce the defects of a memory device and improve the yield rate of the NOR flash memory.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: September 13, 2011
    Assignee: EON Silicon Solutions Inc.
    Inventors: Sheng-Da Liu, Yider Wu
  • Patent number: 8012825
    Abstract: In a method of manufacturing a double-implant NOR flash memory structure, a phosphorus ion implantation process is performed, so that a P-doped drain region is formed in a semiconductor substrate between two gate structures to overlap with a highly-doped drain (HDD) region and a lightly-doped drain (LDD) region. Therefore, the electric connection at a junction between the HDD region and the LDD region is enhanced and the carrier mobility in the memory is not lowered while the problems of short channel effect and punch-through of LDD region are solved.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: September 6, 2011
    Assignee: EON Silicon Solutions Inc.
    Inventors: Yider Wu, Yung-Chung Lee, Yi-Hsiu Chen
  • Patent number: 8008692
    Abstract: A semiconductor memory structure with stress regions includes a substrate defining a first and a second device zone; a first and a second stress region formed in each of the first and second device zone to yield stress different in level; a barrier plug separating the two device zones from each other; and a plurality of oxide spacers being located between the first stress regions and the barrier plug while in direct contact with the first stress regions. Due to the stress yielded at the stress regions, increased carrier mobility and accordingly, increased reading current can be obtained, and only a relatively lower reading voltage is needed to obtain an initially required reading current. As a result, the probability of stress-induced leakage current is reduced to enhance the data retention ability.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: August 30, 2011
    Assignee: EON Silicon Solution Inc.
    Inventors: Hung-Wei Chen, Yider Wu
  • Patent number: 7939423
    Abstract: A non-volatile semiconductor manufacturing method comprises the steps of making element isolation/insulation films that partitions element-forming regions in a semiconductor substrate; stacking a floating gate on the semiconductor substrate via a first gate insulating film; stacking a second gate insulating film formed on the floating gate, and stacking a control gate formed on the floating gate via the second gate insulating film, and self-aligning source and drain diffusion area with the control gate. In the process of stacking a floating gate by partially etching a field oxide film in a select gate area, followed by floating gate formed in a element-forming region and select gate region, and followed by a chemical mechanical polish(CMP) process, both floating gate and select gate is hereby formed simultaneously. Thereby, when memory cells are miniaturized, the invention allows the process to be simple and reduce the defect density.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: May 10, 2011
    Assignee: Eon Silicon Solution Inc.
    Inventor: Yider Wu