Abstract: A method includes receiving a netlist for a chip including a bus and determining, by one or more processors and based on the netlist, a first routing topology for the bus and through a routing region of the chip by comparing a demand of the bus to a capacity of a plurality of cells of the routing region. The method also includes generating a layout for the chip based on the first routing topology.

Abstract: A method includes receiving a netlist for a chip including a bus and determining, by one or more processors and based on the netlist, a first routing topology for the bus and through a routing region of the chip by comparing a demand of the bus to a capacity of a plurality of cells of the routing region. The method also includes generating a layout for the chip based on the first routing topology.

Abstract: For global routing using a graphics processing unit (GPU), a method routes a net of node interconnections for a semiconductor design. In addition, the method decomposes the net into subnets. Each subnet has no shared paths. The method further identifies a congested region of the routed net that exceeds routing capacities. In addition, the method correlates the congested region with a plurality of first subnets with workloads within the congested region. The method routes the subnets in parallel using the GPU.

Abstract: For global routing using a graphics processing unit (GPU), a method routes a net of node interconnections for a semiconductor design. In addition, the method decomposes the net into subnets. Each subnet has no shared paths. The method further identifies a congested region of the routed net that exceeds routing capacities. In addition, the method correlates the congested region with a plurality of first subnets with workloads within the congested region. The method routes the subnets in parallel using the GPU.

Abstract: Circuit floorplanning is performed on a combination central processing unit and multiprocessor. A B*-tree data structure of a floorplan and circuit related constants reside in a central processing unit data storage. The B* tree structure of a floorplan along and said circuit related constants are copied to a multiprocessor data storage where multiple thread blocks, each consisting of a single thread, copy the tree to their own shared memories. The multiprocessor concurrently evaluates different moves in different thread blocks. The multiprocessor then evaluates objective function results and stores those results. The best result for floorplanning is selected from the multiple circuit evaluations.

Abstract: Circuit floorplanning is performed on a combination central processing unit and multiprocessor. A B*-tree data structure of a floorplan and circuit related constants reside in a central processing unit data storage. The B* tree structure of a floorplan along and said circuit related constants are copied to a multiprocessor data storage where multiple thread blocks, each consisting of a single thread, copy the tree to their own shared memories. The multiprocessor concurrently evaluates different moves in different thread blocks. The multiprocessor then evaluates objective function results and stores those results. The best result for floorplanning is selected from the multiple circuit evaluations.