Patents by Inventor Yiding Wu

Yiding Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7864834
    Abstract: A method of estimating jitter for a DFS can include determining a plurality of linear equations, wherein each linear equation corresponds to, at least in part, a combination of multiplier and divisor attributes for setting an output frequency of the DFS, identifying maximum and minimum values for the slope component and the vertical axis intercept component from the plurality of linear equations, providing an equation for determining minimum jitter given, at least in part, an input frequency, and providing an equation for determining maximum jitter given, at least in part, an input frequency. A linear equation can be derived for estimating jitter of the DFS according to a specified input frequency and a specified value of the divisor attribute of the DFS. The linear equation further can depend upon the minimum jitter and the maximum jitter.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: January 4, 2011
    Assignee: Xilinx, Inc.
    Inventor: Yiding Wu
  • Patent number: 7437633
    Abstract: Method and apparatus for testing duty cycle at an input/output node is described. A test signal is generated having a non-zero frequency and a duty cycle. The test signal is sampled using a sampling signal. The phase of the sampling signal is shifted to detect a first level change in the sampled test signal. The phase of the sampling signal is then shifted to detect a second level change in the sampled test signal. The duty cycle of the test signal is computed using a phase indicator of the sampling signal at the first level change and a phase indicator of the sampling signal at the second level change.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: October 14, 2008
    Assignee: XILINX, Inc.
    Inventors: Austin H. Lesea, Yiding Wu
  • Patent number: 7266740
    Abstract: Methods of testing a digital frequency synthesizer (DFS) having a programmable multiplier M and divider D. The full set of tests (wherein every value of M and D is tested) is reduced to a smaller set of tests in which each M/D ratio is tested to a specified resolution. A resolution and minimum and maximum values for M, D, and M/D are specified. An array is allocated, each M/D ratio having a corresponding location in the array, up to the specified resolution. For each MD pair meeting the specified criteria, an M/D ratio is calculated and idealized to the specified resolution, and the MD pair is stored in the corresponding array location. The result is an array of MD pairs that includes zero or one MD pair for each M/D ratio. Thus, by testing each MD pair within the array, all permissible permutations of the input clock frequency are tested.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: September 4, 2007
    Assignee: Xilinx, Inc.
    Inventor: Yiding Wu
  • Patent number: 6836864
    Abstract: Methods of testing a digital frequency synthesizer (DFS) having a programmable multiplier M and divider D. The full set of tests (wherein every value of M and D is tested) is reduced to a smaller set of tests in which each M/D ratio is tested to a specified resolution. A resolution and minimum and maximum values for M, D, and M/D are specified. An array is allocated, each M/D ratio having a corresponding location in the array, up to the specified resolution. For each MD pair meeting the specified criteria, an M/D ratio is calculated and idealized to the specified resolution, and the MD pair is stored in the corresponding array location. The result is an array of MD pairs that includes zero or one MD pair for each M/D ratio. Thus, by testing each MD pair within the array, all permissible permutations of the input clock frequency are tested.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: December 28, 2004
    Assignee: Xilinx, Inc.
    Inventor: Yiding Wu
  • Patent number: 6329833
    Abstract: A measurement system is provided for measuring Vil and Vih of integrated circuits (ICs). The measurement system includes a computer that transmits a control signal to a power supply, which in turn transmits a corresponding applied voltage to the input terminal of an IC. The output terminal of the IC is connected to a parallel port of the computer, thereby forming a feedback loop that allows automatic measurement of Vil and Vih.
    Type: Grant
    Filed: February 24, 1999
    Date of Patent: December 11, 2001
    Assignee: Xilinx, Inc.
    Inventor: Yiding Wu
  • Patent number: 6167001
    Abstract: A microelectronic device such as a Field-Programmable Gate Array (FPGA) includes a large number of elements which can be individually configured or programmed to provide a desired logical functionality. Input and output pins enable external connection of the elements. Each element is configurable to produce an output in response to a first pulse which is applied more than a minimum length of time after a second pulse. The first pulse can be a clock pulse, and the second pulse can be a data pulse, in which case the minimum length of time is the setup time for the element. Each element of a device is tested by repeatedly applying first and second pulses to the device with a delay of the second pulse relative to the first pulse being progressively changed from a first value until a second value corresponding to the minimum length of time is reached as indicated by a transition between the output being produced and the output not being produced.
    Type: Grant
    Filed: January 26, 1999
    Date of Patent: December 26, 2000
    Assignee: Xilinx, Inc.
    Inventor: Yiding Wu