Abstract: Certain aspects relate to a semiconductor die. The semiconductor die includes a voltage-controlled oscillator (VCO), wherein the VCO includes a resonant capacitor, and a resonant inductor coupled in parallel with the resonant capacitor. The resonant inductor includes a first elongated portion and a second elongated portion that are parallel with each other. The semiconductor die also includes a voltage supply line configured to route a supply voltage to the VCO, wherein the voltage supply line includes a first portion that runs parallel with the first and second elongated portions of the resonant inductor and is located between the first and second elongated portions of the resonant inductor.

Abstract: The disclosure provides a device for impedance matching and switching for coupling a transmit path and a receive path of a transceiver to at least one antenna. The device can have an on-chip matching circuitry disposed within a chip and off-chip matching circuitry disposed outside the chip but coupled to the on-chip matching circuitry. The device can have a controller coupled to the on-chip matching circuitry configured to switch the on-chip matching circuitry to provide matched impedance for the transmit path in a transmit mode and matched impedance for the receive path in a receive mode. The off-chip matching circuitry can provide high impedance in the receive path in the transmit mode and provide high impedance in the transmit path in the receive mode. The resonant matching circuit can also have an antenna node coupling the transmit path and the receive path to the at least one antenna.

Abstract: The disclosure is directed to compensating for frequency drift in a voltage-controlled oscillator (VCO). Example methods and systems are described which may detect a signal edge associated with a transceiver, and determine whether one or more lock quality signals indicate that the VCO frequency is outside of an specified range, indicating an unacceptable amount of frequency drift. A frequency tuning setting of the VCO may be adjusted based on the one or more lock quality signals, and a determination may be made whether or not the one or more lock quality signals indicate that the VCO frequency has returned to the specified range. The adjustment of the frequency tuning setting of the VCO may be repeated until the VCO frequency returns to the specified range.

Abstract: An integrated circuit package includes an inductance loop formed from a connection of bonding wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a bonding pad on the integrated circuit chip to an I/O pin of the package and a second wire which connects the same bonding pad to the same pin. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization.

Abstract: Embodiments of an RFIC and methods for same and mobile terminals can internally reduce an input voltage to provide a prescribed voltage to a radio frequency transceiver. Embodiments of an RFIC can have a high efficiency and/or a low noise. In one embodiment, a device can include a PMIC and an RFIC. The RFIC can include an RF transceiver to carry out an RF transmission and an RF reception, a DC-DC converter to lower a voltage provided by the PMIC, and an LDO regulator to regulate the lowered voltage to a fixed voltage used by the RF transceiver.

Abstract: An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from first and second wires which connect a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a third and fourth wires which connect a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a third conductor between the pins. The third conductor may include one or more bonding wires and the I/O pins are preferably ones which are adjacent one another. However, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors. In another embodiment, connection between the first and second I/O pins is established by making the I/O pins have a unitary construction.

Abstract: The application discloses system and method embodiments related to a frequency synthesizer. Embodiments of a frequency synthesizer can have a low phase noise and a narrow channel spacing. Embodiments of a frequency synthesizer can use two phase locked loops. One embodiment of a frequency synthesizer can include a reference frequency oscillator for outputting a signal having a reference frequency, an integer-N phase locked loop to generate a first output frequency signal based on the reference frequency signal, a fractional-N phase locked loop to generate a second output frequency based on the reference frequency signal and a circuit to generate an output frequency signal by combining the first output frequency and the second output frequency.

Abstract: A sigma-delta based phase lock loop device is provided that includes a phase frequency detector (PFD), a charge pump and a voltage controlled oscillator. The PFD to receive a reference signal and a feedback signal and to output signals based on a comparison of the reference signal and the feedback signal. The charge pump to output a charge based on the output signals from the PFD. The charge pump including a first current source to apply a fixed amount of current and a second current source to apply a variable amount of current. The voltage controlled oscillator to output a clock signal based on the received charge from the charge pump.

Abstract: An LC-VCO includes a multivibrator which outputs a frequency signal, a fine tuning circuit which tunes the frequency signal by a first amount, a coarse tuning circuit which tunes the frequency signal by a second amount, and a control circuit which controls the fine and coarse tuning circuits. The coarse tuning circuit is formed from one or more capacitive arrays and the fine tuning circuit is formed from one or more varactors. The capacitive arrays are preferably controlled by a digital signal, where each bit selectively couples a respective capacitor to the multivibrator. An analog signal controls the value of the varactors. The capacitive arrays and varactors charge and discharge an inducator in the multivibrator to tune the frequency signal. The VCO may be incorporated within a phase-locked loop, where the capacitors may be assigned different weight and/or redundancy values to tune an output frequency signal.

Abstract: The application discloses system and method embodiments related to a frequency synthesizer. Embodiments of a frequency synthesizer can have a low phase noise and a narrow channel spacing. Embodiments of a frequency synthesizer can use two phase locked loops. One embodiment of a frequency synthesizer can include a reference frequency oscillator for outputting a signal having a reference frequency, an integer-N phase locked loop to generate a first output frequency signal based on the reference frequency signal, a fractional-N phase locked loop to generate a second output frequency based on the reference frequency signal and a circuit to generate an output frequency signal by combining the first output frequency and the second output frequency.

Abstract: Embodiments of an RFIC and methods for same and mobile terminals can internally reduce an input voltage to provide a prescribed voltage to a radio frequency transceiver. Embodiments of an RFIC can have a high efficiency and/or a low noise. In one embodiment, a device can include a PMIC and an RFIC. The RFIC can include an RF transceiver to carry out an RF transmission and an RF reception, a DC-DC converter to lower a voltage provided by the PMIC, and an LDO regulator to regulate the lowered voltage to a fixed voltage used by the RF transceiver.

Abstract: An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a second wire which connects a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a conductive bridge between the pins. The bridge may be formed by making the I/O pins have a unitary construction. In another embodiment, the bridge is formed by a metallization layer located either on the surface of the package substrate or within this substrate. The I/O pins are preferably ones which are adjacent one another; however, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors.

Abstract: An integrated circuit package includes an inductance loop formed from a connection of bonding wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a bonding pad on the integrated circuit chip to an I/O pin of the package and a second wire which connects the same bonding pad to the same pin. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization.

Abstract: A sigma-delta based phase lock loop device is provided that includes a phase frequency detector (PFD), a charge pump and a voltage controlled oscillator. The PFD to receive a reference signal and a feedback signal and to output signals based on a comparison of the reference signal and the feedback signal. The charge pump to output a charge based on the output signals from the PFD. The charge pump including a first current source to apply a fixed amount of current and a second current source to apply a variable amount of current. The voltage controlled oscillator to output a clock signal based on the received charge from the charge pump.

Abstract: An LC-VCO includes a multivibrator which outputs a frequency signal, a fine tuning circuit which tunes the frequency signal by a first amount, a coarse tuning circuit which tunes the frequency signal by a second amount, and a control circuit which controls the fine and coarse tuning circuits. The coarse tuning circuit is formed from one or more capacitive arrays and the fine tuning circuit is formed from one or more varactors. The capacitive arrays are preferably controlled by a digital signal, where each bit selectively couples a respective capacitor to the multivibrator. An analog signal controls the value of the varactors. The capacitive arrays and varactors charge and discharge an inducator in the multivibrator to tune the frequency signal. The VCO may be incorporated within a phase-locked loop, where the capacitors may be assigned different weight and/or redundancy values to tune an output frequency signal.

Abstract: A system and method for improving the signal-to-noise ratio of a frequency generator suppresses phase noise and noise generated from mismatches in the internal generator circuits. This is accomplished using a modulation scheme which shifts spurious noise signals outside the loop bandwidth of the generator. When shifted in this manner, the noise signals maybe removed entirely or to any desired degree using, for example, a filter located along the signal path of the generator. In one embodiment, a Sigma-Delta modulator controls the value of a pulse-swallow frequency divider situated along a feedback path of a phase-locked loop to achieve a desired level of noise suppression. In another embodiment, a reference signal input into a phase-locked loop is modulated to effect noise suppression. In another embodiment, the foregoing forms of modulation are combined to accomplish the desired frequency shift.

Abstract: A voltage-controlled oscillator including an active oscillator circuit, an inductor, and capacitive circuits is disclosed. The capacitive circuits are selectively turned on and off to control the frequency of the voltage-controlled oscillator. Particularly, the inductor and the capacitors in the capacitive circuits form LC circuits that provide feedback to the active oscillator circuit. To avoid damage to the switches in the capacitive circuits, the capacitive circuits further comprise resistors. The resistors can be configured in several different ways so that the voltage-controlled oscillator can have a high degree of reliability, and a wide tuning range with constant phase noise performance.

Abstract: An integrated circuit package includes an inductance loop formed from a connection of bonding wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a bonding pad on the integrated circuit chip to an I/O pin of the package and a second wire which connects the same bonding pad to the same pin. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization.

Abstract: An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a second wire which connects a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a conductive bridge between the pins. The bridge may be formed by making the I/O pins have a unitary construction. In another embodiment, the bridge is formed by a metallization layer located either on the surface of the package substrate or within this substrate. The I/O pins are preferably ones which are adjacent one another; however, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors.

Abstract: An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from first and second wires which connect a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a third and fourth wires which connect a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a third conductor between the pins. The third conductor may include one or more bonding wires and the I/O pins are preferably ones which are adjacent one another. However, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors. In another embodiment, connection between the first and second I/O pins is established by making the I/O pins have a unitary construction.