Patents by Inventor Yien Sien Khoo

Yien Sien Khoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10943856
    Abstract: Described examples include a system in package (SIP) device, including: a first leadframe having a first surface and a second surface opposite the first surface; an integrated circuit die including solder bumps on a first surface and having a second opposite surface, the solder bumps mounted to the second surface of the first leadframe; a second leadframe having a first surface including a die pad portion, and a second opposite surface, the die pad portion attached to the second surface of the integrated circuit die; and an inductor mounted to the first surface of the first leadframe, the inductor having terminals with exterior portions electrically connected and mechanically connected to the first surface of the first leadframe, the inductor terminals spaced from one another by a portion of an inductor body, the portion of the inductor body between the inductor terminals spaced from the first surface of the first leadframe by a gap of at least 100 ?ms.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: March 9, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yien Sien Khoo, Siew Kee Lee
  • Publication number: 20190326203
    Abstract: Described examples include a system in package (SIP) device, including: a first leadframe having a first surface and a second surface opposite the first surface; an integrated circuit die including solder bumps on a first surface and having a second opposite surface, the solder bumps mounted to the second surface of the first leadframe; a second leadframe having a first surface including a die pad portion, and a second opposite surface, the die pad portion attached to the second surface of the integrated circuit die; and an inductor mounted to the first surface of the first leadframe, the inductor having terminals with exterior portions electrically connected and mechanically connected to the first surface of the first leadframe, the inductor terminals spaced from one another by a portion of an inductor body, the portion of the inductor body between the inductor terminals spaced from the first surface of the first leadframe by a gap of at least 100 ?ms.
    Type: Application
    Filed: July 2, 2019
    Publication date: October 24, 2019
    Inventors: Yien Sien Khoo, Siew Kee Lee
  • Patent number: 10340210
    Abstract: Described examples include a system in package (SIP) device, including: a first leadframe having a first surface and a second surface opposite the first surface; an integrated circuit die including solder bumps on a first surface and having a second opposite surface, the solder bumps mounted to the second surface of the first leadframe; a second leadframe having a first surface including a die pad portion, and a second opposite surface, the die pad portion attached to the second surface of the integrated circuit die; and an inductor mounted to the first surface of the first leadframe, the inductor having terminals with exterior portions electrically connected and mechanically connected to the first surface of the first leadframe, the inductor terminals spaced from one another by a portion of an inductor body, the portion of the inductor body between the inductor terminals spaced from the first surface of the first leadframe by a gap of at least 100 ?ms.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 2, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yien Sien Khoo, Siew Kee Lee
  • Publication number: 20180082930
    Abstract: Described examples include a system in package (SIP) device, including: a first leadframe having a first surface and a second surface opposite the first surface; an integrated circuit die including solder bumps on a first surface and having a second opposite surface, the solder bumps mounted to the second surface of the first leadframe; a second leadframe having a first surface including a die pad portion, and a second opposite surface, the die pad portion attached to the second surface of the integrated circuit die; and an inductor mounted to the first surface of the first leadframe, the inductor having terminals with exterior portions electrically connected and mechanically connected to the first surface of the first leadframe, the inductor terminals spaced from one another by a portion of an inductor body, the portion of the inductor body between the inductor terminals spaced from the first surface of the first leadframe by a gap of at least 100 ?ms.
    Type: Application
    Filed: August 31, 2017
    Publication date: March 22, 2018
    Inventors: Yien Sien Khoo, Siew Kee Lee
  • Patent number: 9275983
    Abstract: A method of making an integrated circuit (IC) package including electrically and physically attaching a die to an interposer, attaching the interposer to a bottom leadframe, attaching a discrete circuit component to the interposer and attaching a top leadframe to the bottom leadframe.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: March 1, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Lee Han Meng@ Eugene Lee, Anis Fauzi bin Abdul Aziz, Yien Sien Khoo
  • Publication number: 20150243641
    Abstract: A method of making an integrated circuit (IC) package including electrically and physically attaching a die to an interposer, attaching the interposer to a bottom leadframe, attaching a discrete circuit component to the interposer and attaching a top leadframe to the bottom leadframe.
    Type: Application
    Filed: May 7, 2015
    Publication date: August 27, 2015
    Inventors: Lee Han Meng@ Eugene Lee, Anis Fauzi bin Abdul Aziz, Yien Sien Khoo
  • Patent number: 9029990
    Abstract: An integrated circuit (IC) package including a bottom leadframe, an interposer mounted on the bottom leadframe, a flipchip die mounted on the interposer and a top leadframe electrically connected to the interposer. Also, a method of making an integrated circuit (IC) package including electrically and physically attaching a die to an interposer, attaching the interposer to a bottom leadframe, attaching a discrete circuit component to the interposer and attaching a top leadframe to the bottom leadframe.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: May 12, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Lee Hang Meng@Eugene Lee, Anis Fauzi Abdul Aziz, Yien Sien Khoo
  • Patent number: 8779566
    Abstract: In one aspect of the invention, an integrated circuit package is described. The integrated circuit package includes a substrate formed from a dielectric material that includes multiple electrical contacts and conductive paths. An upper lead frame is attached with and underlies the substrate. The upper lead frame is electrically connected with at least one of the contacts on the substrate. The active surface of an integrated circuit die is electrically and physically coupled to the upper lead frame through multiple electrical connectors. A lower lead frame may be attached with the back surface of the integrated circuit die. A passive device is positioned on and electrically connected with one of the contacts on the substrate and/or the upper lead frame.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: July 15, 2014
    Assignee: National Semiconductor Corporation
    Inventors: Lee Han Meng @ Eugene Lee, Yien Sien Khoo, Kuan Yee Woo
  • Publication number: 20140191378
    Abstract: An integrated circuit (IC) package including a bottom leadframe, an interposer mounted on the bottom leadframe, a flipchip die mounted on the interposer and a top leadframe electrically connected to the interposer. Also, a method of making an integrated circuit (IC) package including electrically and physically attaching a die to an interposer, attaching the interposer to a bottom leadframe, attaching a discrete circuit component to the interposer and attaching a top leadframe to the bottom leadframe.
    Type: Application
    Filed: January 4, 2013
    Publication date: July 10, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Han Meng@Eugene Lee Lee, Anis Fauzi Abdul Aziz, Yien Sien Khoo
  • Publication number: 20130045572
    Abstract: In one aspect of the invention, an integrated circuit package is described. The integrated circuit package includes a substrate formed from a dielectric material that includes multiple electrical contacts and conductive paths. An upper lead frame is attached with and underlies the substrate. The upper lead frame is electrically connected with at least one of the contacts on the substrate. The active surface of an integrated circuit die is electrically and physically coupled to the upper lead frame through multiple electrical connectors. A lower lead frame may be attached with the back surface of the integrated circuit die. A passive device is positioned on and electrically connected with one of the contacts on the substrate and/or the upper lead frame.
    Type: Application
    Filed: August 15, 2011
    Publication date: February 21, 2013
    Applicant: NATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Lee Han Meng @ Eugene Lee, Yien Sien Khoo, Kuan Yee Woo