Patents by Inventor Yien Sien Khoo
Yien Sien Khoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10943856Abstract: Described examples include a system in package (SIP) device, including: a first leadframe having a first surface and a second surface opposite the first surface; an integrated circuit die including solder bumps on a first surface and having a second opposite surface, the solder bumps mounted to the second surface of the first leadframe; a second leadframe having a first surface including a die pad portion, and a second opposite surface, the die pad portion attached to the second surface of the integrated circuit die; and an inductor mounted to the first surface of the first leadframe, the inductor having terminals with exterior portions electrically connected and mechanically connected to the first surface of the first leadframe, the inductor terminals spaced from one another by a portion of an inductor body, the portion of the inductor body between the inductor terminals spaced from the first surface of the first leadframe by a gap of at least 100 ?ms.Type: GrantFiled: July 2, 2019Date of Patent: March 9, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yien Sien Khoo, Siew Kee Lee
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Publication number: 20190326203Abstract: Described examples include a system in package (SIP) device, including: a first leadframe having a first surface and a second surface opposite the first surface; an integrated circuit die including solder bumps on a first surface and having a second opposite surface, the solder bumps mounted to the second surface of the first leadframe; a second leadframe having a first surface including a die pad portion, and a second opposite surface, the die pad portion attached to the second surface of the integrated circuit die; and an inductor mounted to the first surface of the first leadframe, the inductor having terminals with exterior portions electrically connected and mechanically connected to the first surface of the first leadframe, the inductor terminals spaced from one another by a portion of an inductor body, the portion of the inductor body between the inductor terminals spaced from the first surface of the first leadframe by a gap of at least 100 ?ms.Type: ApplicationFiled: July 2, 2019Publication date: October 24, 2019Inventors: Yien Sien Khoo, Siew Kee Lee
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Patent number: 10340210Abstract: Described examples include a system in package (SIP) device, including: a first leadframe having a first surface and a second surface opposite the first surface; an integrated circuit die including solder bumps on a first surface and having a second opposite surface, the solder bumps mounted to the second surface of the first leadframe; a second leadframe having a first surface including a die pad portion, and a second opposite surface, the die pad portion attached to the second surface of the integrated circuit die; and an inductor mounted to the first surface of the first leadframe, the inductor having terminals with exterior portions electrically connected and mechanically connected to the first surface of the first leadframe, the inductor terminals spaced from one another by a portion of an inductor body, the portion of the inductor body between the inductor terminals spaced from the first surface of the first leadframe by a gap of at least 100 ?ms.Type: GrantFiled: August 31, 2017Date of Patent: July 2, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yien Sien Khoo, Siew Kee Lee
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Publication number: 20180082930Abstract: Described examples include a system in package (SIP) device, including: a first leadframe having a first surface and a second surface opposite the first surface; an integrated circuit die including solder bumps on a first surface and having a second opposite surface, the solder bumps mounted to the second surface of the first leadframe; a second leadframe having a first surface including a die pad portion, and a second opposite surface, the die pad portion attached to the second surface of the integrated circuit die; and an inductor mounted to the first surface of the first leadframe, the inductor having terminals with exterior portions electrically connected and mechanically connected to the first surface of the first leadframe, the inductor terminals spaced from one another by a portion of an inductor body, the portion of the inductor body between the inductor terminals spaced from the first surface of the first leadframe by a gap of at least 100 ?ms.Type: ApplicationFiled: August 31, 2017Publication date: March 22, 2018Inventors: Yien Sien Khoo, Siew Kee Lee
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Patent number: 9275983Abstract: A method of making an integrated circuit (IC) package including electrically and physically attaching a die to an interposer, attaching the interposer to a bottom leadframe, attaching a discrete circuit component to the interposer and attaching a top leadframe to the bottom leadframe.Type: GrantFiled: May 7, 2015Date of Patent: March 1, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Lee Han Meng@ Eugene Lee, Anis Fauzi bin Abdul Aziz, Yien Sien Khoo
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Publication number: 20150243641Abstract: A method of making an integrated circuit (IC) package including electrically and physically attaching a die to an interposer, attaching the interposer to a bottom leadframe, attaching a discrete circuit component to the interposer and attaching a top leadframe to the bottom leadframe.Type: ApplicationFiled: May 7, 2015Publication date: August 27, 2015Inventors: Lee Han Meng@ Eugene Lee, Anis Fauzi bin Abdul Aziz, Yien Sien Khoo
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Patent number: 9029990Abstract: An integrated circuit (IC) package including a bottom leadframe, an interposer mounted on the bottom leadframe, a flipchip die mounted on the interposer and a top leadframe electrically connected to the interposer. Also, a method of making an integrated circuit (IC) package including electrically and physically attaching a die to an interposer, attaching the interposer to a bottom leadframe, attaching a discrete circuit component to the interposer and attaching a top leadframe to the bottom leadframe.Type: GrantFiled: January 4, 2013Date of Patent: May 12, 2015Assignee: Texas Instruments IncorporatedInventors: Lee Hang Meng@Eugene Lee, Anis Fauzi Abdul Aziz, Yien Sien Khoo
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Patent number: 8779566Abstract: In one aspect of the invention, an integrated circuit package is described. The integrated circuit package includes a substrate formed from a dielectric material that includes multiple electrical contacts and conductive paths. An upper lead frame is attached with and underlies the substrate. The upper lead frame is electrically connected with at least one of the contacts on the substrate. The active surface of an integrated circuit die is electrically and physically coupled to the upper lead frame through multiple electrical connectors. A lower lead frame may be attached with the back surface of the integrated circuit die. A passive device is positioned on and electrically connected with one of the contacts on the substrate and/or the upper lead frame.Type: GrantFiled: August 15, 2011Date of Patent: July 15, 2014Assignee: National Semiconductor CorporationInventors: Lee Han Meng @ Eugene Lee, Yien Sien Khoo, Kuan Yee Woo
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Publication number: 20140191378Abstract: An integrated circuit (IC) package including a bottom leadframe, an interposer mounted on the bottom leadframe, a flipchip die mounted on the interposer and a top leadframe electrically connected to the interposer. Also, a method of making an integrated circuit (IC) package including electrically and physically attaching a die to an interposer, attaching the interposer to a bottom leadframe, attaching a discrete circuit component to the interposer and attaching a top leadframe to the bottom leadframe.Type: ApplicationFiled: January 4, 2013Publication date: July 10, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Han Meng@Eugene Lee Lee, Anis Fauzi Abdul Aziz, Yien Sien Khoo
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Publication number: 20130045572Abstract: In one aspect of the invention, an integrated circuit package is described. The integrated circuit package includes a substrate formed from a dielectric material that includes multiple electrical contacts and conductive paths. An upper lead frame is attached with and underlies the substrate. The upper lead frame is electrically connected with at least one of the contacts on the substrate. The active surface of an integrated circuit die is electrically and physically coupled to the upper lead frame through multiple electrical connectors. A lower lead frame may be attached with the back surface of the integrated circuit die. A passive device is positioned on and electrically connected with one of the contacts on the substrate and/or the upper lead frame.Type: ApplicationFiled: August 15, 2011Publication date: February 21, 2013Applicant: NATIONAL SEMICONDUCTOR CORPORATIONInventors: Lee Han Meng @ Eugene Lee, Yien Sien Khoo, Kuan Yee Woo