Patents by Inventor Yifan Gu
Yifan Gu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230385285Abstract: A computer-implemented method executed using a first networked computer and comprising: receiving a digitally stored workflow pattern that specifies at least an input data source, a data transformation process, and an output data destination, the workflow pattern comprising a structured plurality of name declarations and value specifications that are human readable and machine readable, the data transformation process specified in the workflow pattern including one or more references to processing logic, a processing logic source outside the workflow pattern at which the processing logic is stored, and one or more available process engines that are capable of processing the processing logic; machine parsing the workflow pattern and dividing the workflow pattern into a plurality of execution units, each execution unit being associated with a particular process engine among the one or more available process engines; accessing the input data source specified in the workflow pattern and loading at least a portionType: ApplicationFiled: May 31, 2022Publication date: November 30, 2023Inventors: Uday Rajanna, Srinivasan Hariharan, Bhargavi Damodaran, Yifan Gu, Puneet Bysani, Lakshmi Ranjani Venkateswaran
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Publication number: 20230385266Abstract: A computer-implemented method executed using a first networked computer and comprising receiving a digitally stored workflow pattern that specifies at least an input data source, a data transformation process, an output data destination, a data quality assertion and a data quality source; the workflow pattern comprising a structured plurality of name declarations and value specifications that are human readable and machine readable; the data transformation process specified in the workflow pattern including one or more references to processing logic, a processing logic source outside the workflow pattern at which the processing logic is stored, and one or more available process engines that are capable of processing the processing logic; machine parsing the workflow pattern and dividing the workflow pattern into a plurality of execution units, each execution unit being associated with a particular process engine among the one or more available process engines; accessing the input data source specified in theType: ApplicationFiled: May 31, 2022Publication date: November 30, 2023Inventors: Uday Rajanna, Yifan Gu, Benjamin Cohen, Puneet Bysani, Lakshmi Ranjani Venkateswaran
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Patent number: 11794163Abstract: The present invention provides a metal-organic framework material for the adsorptive separation of acetylene/ethylene mixture and preparation method therefor. The metal-organic framework material is named TJE-2 with a chemical formula of [Ni(pyc)(apyz)]n, wherein, Ni represents nickel as a metal center, pyc represents the organic ligand 1H-pyrazole-4-carboxylic acid, and apyz represents the organic ligand 2-aminopyrazine. The preparation method is as follows: thoroughly dissolving pyc, apyz and Ni(NO3)2ยท6H2O, transferring the mixture to a pressure-resistant closed container for heating reaction, followed by solvent exchange and activation to obtain a homogeneous powder material. The ultra-microporous metal-organic framework material prepared by the present invention features a significantly high C2H2 adsorption capacity, good selectivity, and low raw material costs, and therefore can realize C2H2/C2H4 separation at lower costs.Type: GrantFiled: January 5, 2023Date of Patent: October 24, 2023Assignee: TONGJI UNIVERSITYInventors: Fengting Li, Yifan Gu, Hengcong Huang, Ying Wang
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Publication number: 20230312360Abstract: Disclosed is a method for continuously producing polyaluminum chloride from aluminum slag, comprising: blending the aluminum slag with water into a slurry in a mixing tank; pumping the slurry and a sodium hydroxide solution into a first mixing reactor; introducing the mixture obtained in the first mixing reactor into a second mixing reactor and pumping hydrochloric acid into the second mixing reactor; and filtering the resulting mixture and allowing filtrate for ripening, polymerization and sedimentation to obtain liquid polyaluminum chloride; wherein each of the reactors is pipeline-shaped, arranged horizontally and provided with a spiral conveyor shaft inside which is arranged horizontally and configured to stir and convey the mixture in a pipeline. This method realizes a continuous treatment of aluminum slag together with a continuous recovery of ammonia nitrogen and produces PAC, thereby achieving resourceful utilization and improved operability.Type: ApplicationFiled: June 24, 2022Publication date: October 5, 2023Inventors: Fengting Li, Ying Wang, Yifan Gu, Tao Kong, Zekun Li
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Publication number: 20220183644Abstract: A method, an apparatus and a system for conveniently measuring coronary artery vascular evaluation parameters are provided by the disclosure.Type: ApplicationFiled: March 2, 2022Publication date: June 16, 2022Applicant: SUZHOU RAINMED MEDICAL TECHNOLOGY CO., LTD.Inventors: Guangzhi LIU, Zhiyuan WANG, Yifan GU, Zhiting WANG, Yong HUO, Yanjun GONG, Jianping LI, Tieci YI
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Patent number: 10461757Abstract: An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a not-and (NAND) operation according to the first sampled signal and the second sampled signal to produce an activation signal for activating a frequency adjustment for the clock signal.Type: GrantFiled: December 29, 2016Date of Patent: October 29, 2019Assignee: Futurewei Technologies, Inc.Inventors: Liang Gu, Yuming Cao, Gong Lei, Yen Dang, Yifan Gu, Hungyi Lee, Mamatha Deshpande, Shou-Po Shih, Yan Duan
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Patent number: 10396805Abstract: A reference-less frequency detector circuit includes a sampling circuit that is configured to generate a frequency control voltage and a switch circuit control signal based on a frequency difference between a clock signal frequency and an input data rate. The frequency control voltage has a frequency down indication and a frequency up indication. A voltage-to-current converter circuit is coupled to the sampling circuit and is configured to convert the frequency control voltage to a frequency control current based on the switch circuit control signal. The voltage-to-current converter circuit includes an output switch circuit controlled by the switch control signal and is configured to have substantially equal respective latencies for the frequency down indication and the frequency up indication.Type: GrantFiled: August 31, 2018Date of Patent: August 27, 2019Assignee: Futurewei Technologies, Inc.Inventors: Liang Gu, Yuming Cao, Yen Dang, Gong Lei, Yifan Gu, Hung-Yi Lee, Mamatha Deshpande, Shou-Po Shih, Miao Liu
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Publication number: 20180375522Abstract: A reference-less frequency detector circuit includes a sampling circuit that is configured to generate a frequency control voltage and a switch circuit control signal based on a frequency difference between a clock signal frequency and an input data rate. The frequency control voltage has a frequency down indication and a frequency up indication. A voltage-to-current converter circuit is coupled to the sampling circuit and is configured to convert the frequency control voltage to a frequency control current based on the switch circuit control signal. The voltage-to-current converter circuit includes an output switch circuit controlled by the switch control signal and is configured to have substantially equal respective latencies for the frequency down indication and the frequency up indication.Type: ApplicationFiled: August 31, 2018Publication date: December 27, 2018Inventors: Liang Gu, Yuming Cao, Yen Dang, Gong Lei, Yifan Gu, Hung-Yi Lee, Mamatha Deshpande, Shou-Po Shih, Miao Liu
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Patent number: 10122348Abstract: A multiplexer comprises: an output circuit comprising a multiplexer output; and a first buffer coupled to the output circuit and comprising: a first selection input configured to receive a first selection signal; a first logical input configured to receive a first logical input signal; and a first ground; wherein the multiplexer is configured to: couple the first logical input to the multiplexer output when the first selection signal is a first value; and couple the first logical input to the first ground when the first selection signal is a second value. A method comprises: receiving a selection signal and a first logical input signal; coupling a first logical input to a multiplexer output when the selection signal is a first value; and coupling the first logical input to a ground when the selection signal is a second value.Type: GrantFiled: March 30, 2016Date of Patent: November 6, 2018Assignee: Futurewei Technologies, Inc.Inventors: Liang Gu, Yuming Cao, Gong Lei, Yen Dang, Yifan Gu, Hungyi Lee, Mamatha Deshpande, Shou-Po Shih, Yan Duan
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Patent number: 10116470Abstract: An apparatus comprising an input port configured to receive an input signal propagated through a transmission link, wherein the transmission link comprises a low-frequency channel loss and a high-frequency channel loss, a continuous-time linear equalization (CTLE) circuit coupled to the input port and configured to produce an output signal according to the input signal by applying a first gain to the input signal at a first frequency to compensate the low-frequency loss, and applying a second gain to the input signal at a second frequency to compensate the high-frequency channel loss, and an output port coupled to the CTLE circuit and configured to output the output signal.Type: GrantFiled: October 28, 2015Date of Patent: October 30, 2018Assignee: Futurewei Technologies, Inc.Inventors: Liang Gu, Yuming Cao, Yen Dang, Gong Lei, Hungyi Lee, Yifan Gu, Mamatha Deshpande, Shou-Po Shih, Yan Duan
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Patent number: 10097190Abstract: A reference-less frequency detector circuit includes a sampling circuit that is configured to generate a frequency control voltage and a switch circuit control signal based on a frequency difference between a clock signal frequency and an input data rate. The frequency control voltage has a frequency down indication and a frequency up indication. A voltage-to-current converter circuit is coupled to the sampling circuit and is configured to convert the frequency control voltage to a frequency control current based on the switch circuit control signal. The voltage-to-current converter circuit includes an output switch circuit controlled by the switch control signal and is configured to have substantially equal respective latencies for the frequency down indication and the frequency up indication.Type: GrantFiled: December 29, 2016Date of Patent: October 9, 2018Assignee: Futurewei Technologies, Inc.Inventors: Liang Gu, Yuming Cao, Yen Dang, Gong Lei, Yifan Gu, Hung-Yi Lee, Mamatha Deshpande, Shou-Po Shih, Miao Liu
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Publication number: 20180175865Abstract: A reference-less frequency detector circuit includes a sampling circuit that is configured to generate a frequency control voltage and a switch circuit control signal based on a frequency difference between a clock signal frequency and an input data rate. The frequency control voltage has a frequency down indication and a frequency up indication. A voltage-to-current converter circuit is coupled to the sampling circuit and is configured to convert the frequency control voltage to a frequency control current based on the switch circuit control signal. The voltage-to-current converter circuit includes an output switch circuit controlled by the switch control signal and is configured to have substantially equal respective latencies for the frequency down indication and the frequency up indication.Type: ApplicationFiled: December 29, 2016Publication date: June 21, 2018Inventors: Liang Gu, Yuming Cao, Yen Dang, Gong Lei, Yifan Gu, Hung-Yi Lee, Mamatha Deshpande, Shou-Po Shih, Miao Liu
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Patent number: 9964832Abstract: An electronic driver circuit for use with a modulator such as a segmented Mach-Zehnder Modulator (MZM) is provided. The electronic driver circuit includes a first delay buffer implemented as a first complementary metal-oxide-semiconductor (CMOS) inverter and a second delay buffer implemented as a second CMOS inverter. The second CMOS inverter follows the first CMOS inverter and has a second gate width smaller than a first gate width of the first CMOS inverter. The first CMOS inverter is configured to produce a first delayed electrical signal from a received electrical signal and the second CMOS inverter is configured to produce a second delayed electrical signal from the first delayed electrical signal produced by the first CMOS inverter.Type: GrantFiled: May 28, 2015Date of Patent: May 8, 2018Assignee: Futurewei Technologies, Inc.Inventors: Morgan Chen, Yifan Gu, Hungyi Lee, Liang Gu, Yen Dang, Gong Lei, Yuming Cao, Xiao Shen, Yu Sheng Bai
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Patent number: 9941958Abstract: An apparatus comprising a semiconductor chip that comprises an optical modulator configured to modulate an optical signal based on a received driver signal, a voltage-mode (VM) driver coupled to the optical modulator and configured to produce a level-shifted driver signal to modulate the optical signal, and a two-stage test interface coupled to the optical modulator and configured to receive and test the level shifted driver signal. The two-stage test interface comprises a voltage equalization stage coupled to an output-terminated buffer stage, the VM driver comprises a two-stage VM Mach-Zehnder modulator (MZM) driver that comprises a pre-driver coupled to a VM level-shifter (VMLS). The apparatus further comprises a resistor coupled to an output of the buffer stage, wherein the resistor comprises an amount of resistance that matches a termination resistance of a test equipment. The termination resistance is about 50 ohm (?).Type: GrantFiled: December 15, 2015Date of Patent: April 10, 2018Assignee: Futurewei Technologies, Inc.Inventors: Liang Gu, Yuming Cao, Yifan Gu, Hungyi Lee, Gong Lei, Yen Dang, Mamatha Deshpande, Shou-Po Shih, Yan Duan
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Patent number: 9838239Abstract: An apparatus comprising a first electrical driver configured to generate a first binary voltage signal according to first data, a second electrical driver configured to generate a second binary voltage signal according to second data, wherein the first data and the second data are different, and a first optical waveguide arm coupled to the first electrical driver and the second electrical driver, wherein the first optical waveguide arm is configured to shift a first phase of a first optical signal propagating along the first optical waveguide arm according to a first voltage difference between the first binary voltage signal and the second binary voltage signal to produce a first multi-level phase-shifted optical signal.Type: GrantFiled: January 7, 2016Date of Patent: December 5, 2017Assignee: Futurewei Technologies, Inc.Inventors: Morgan Chen, Qianfan Xu, Hungyi Lee, Yifan Gu, Liang Gu, Yen Dang, Gong Lei, Yuming Cao, Xiao Shen, Yu Sheng Bai
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Publication number: 20170288652Abstract: A multiplexer comprises: an output circuit comprising a multiplexer output; and a first buffer coupled to the output circuit and comprising: a first selection input configured to receive a first selection signal; a first logical input configured to receive a first logical input signal; and a first ground; wherein the multiplexer is configured to: couple the first logical input to the multiplexer output when the first selection signal is a first value; and couple the first logical input to the first ground when the first selection signal is a second value. A method comprises: receiving a selection signal and a first logical input signal; coupling a first logical input to a multiplexer output when the selection signal is a first value; and coupling the first logical input to a ground when the selection signal is a second value.Type: ApplicationFiled: March 30, 2016Publication date: October 5, 2017Inventors: Liang Gu, Yuming Cao, Gong Lei, Yen Dang, Yifan Gu, Hungyi Lee, Mamatha Deshpande, Shou-Po Shih, Yan Duan
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Publication number: 20170170894Abstract: An apparatus comprising a semiconductor chip that comprises an optical modulator configured to modulate an optical signal based on a received driver signal, a voltage-mode (VM) driver coupled to the optical modulator and configured to produce a level-shifted driver signal to modulate the optical signal, and a two-stage test interface coupled to the optical modulator and configured to receive and test the level shifted driver signal. The two-stage test interface comprises a voltage equalization stage coupled to an output-terminated buffer stage, the VM driver comprises a two-stage VM Mach-Zehnder modulator (MZM) driver that comprises a pre-driver coupled to a VM level-shifter (VMLS). The apparatus further comprises a resistor coupled to an output of the buffer stage, wherein the resistor comprises an amount of resistance that matches a termination resistance of a test equipment. The termination resistance is about 50 ohm (?).Type: ApplicationFiled: December 15, 2015Publication date: June 15, 2017Inventors: Liang Gu, Yuming Cao, Yifan Gu, Hungyi Lee, Gong Lei, Yen Dang, Mamatha Deshpande, Shou-Po Shih, Yan Duan
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Publication number: 20170126443Abstract: An apparatus comprising an input port configured to receive an input signal propagated through a transmission link, wherein the transmission link comprises a low-frequency channel loss and a high-frequency channel loss, a continuous-time linear equalization (CTLE) circuit coupled to the input port and configured to produce an output signal according to the input signal by applying a first gain to the input signal at a first frequency to compensate the low-frequency loss, and applying a second gain to the input signal at a second frequency to compensate the high-frequency channel loss, and an output port coupled to the CTLE circuit and configured to output the output signal.Type: ApplicationFiled: October 28, 2015Publication date: May 4, 2017Inventors: Liang Gu, Yuming Cao, Yen Dang, Gong Lei, Hungyi Lee, Yifan Gu, Mamatha Deshpande, Shou-Po Shih, Yan Duan
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Publication number: 20170126236Abstract: An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a not-and (NAND) operation according to the first sampled signal and the second sampled signal to produce an activation signal for activating a frequency adjustment for the clock signal.Type: ApplicationFiled: December 29, 2016Publication date: May 4, 2017Inventors: Liang Gu, Yuming Cao, Gong Lei, Yen Dang, Yifan Gu, Hungyi Lee, Mamatha Deshpande, Shou-Po Shih, Yan Duan
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Patent number: 9584303Abstract: An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a not-and (NAND) operation according to the first sampled signal and the second sampled signal to produce an activation signal for activating a frequency adjustment for the clock signal.Type: GrantFiled: October 28, 2015Date of Patent: February 28, 2017Assignee: Futurewei Technologies, Inc.Inventors: Liang Gu, Yuming Cao, Gong Lei, Yen Dang, Yifan Gu, Hungyi Lee, Mamatha Deshpande, Shou-Po Shih, Yan Duan