Abstract: A disconnection mechanism, for engaging or disengaging a fixed component and a movable component arranged on a first shaft extending in a first direction. The disconnection mechanism includes a shift fork, connected to the movable component, and constructed to be able to reciprocate linearly in the first direction, so that the movable component is engaged with or disengaged from the fixed component. An actuator includes an output end which rotates about a rotation axis of the actuator at a distance from the rotation axis. A drive rod has a first end rotatably connected to the output end and a second end rotatably connected to the shift fork, so that the output end, when rotating, is able to drive the shift fork to reciprocate linearly.

Abstract: The embodiments of the present disclosure provide a method and a device for generating a call topology. The method comprises generating an attribute information storage queue for each attribute information dimension of the microservice trace information. The method further comprises filtering the attribute information upon receiving a topology generation instruction. The method further comprises generating a call topology using call trace information corresponding to the target attribute information obtained by filtering.

Abstract: Disclosed are an advanced persistent threat (APT) detection method and system based on a continuous-time dynamic heterogeneous graph network (CDHGN). The method includes: selecting network interaction event data, extracting entities from the network interaction event data as source nodes and target nodes, extracting an interaction event occurring between a source node and a target node as an edge, and determining a type and an attribute of a node, a type and an attribute of the edge, and a moment at which an interaction event occurs, to obtain a continuous-time dynamic heterogeneous graph; converting each type of edge in the continuous-time dynamic heterogeneous graph into a vector by a CDHGN encoder, to obtain an embedding representation by a CDHGN decoder to obtain a detection result of whether each type of edge is an abnormal edge, to intercept an APT attack.

Abstract: Provided are a method and a device for information storage. The method includes: obtaining a plurality of pieces of target data, the target data including a plurality of pairs of key-value data; generating, based on an order of the plurality of pieces of target data, a first column storage file that stores key data included in each piece of target data; and generating, based on the order of the plurality of pieces of target data, a second column storage file that stores value data included in each piece of target data; wherein first position information of key data of each piece of the target data in the first column storage file is same as second position information of corresponding value data in the second column storage file.

Abstract: The present invention is concerned with a wireless device comprising: a communication processor; WiFi hardware operable to access a WiFi communication channel; and a computer-readable medium storing instructions, which when executed by the communications processor, cause the communication processor to: execute, in a MAC layer of a communication protocol stack, a channel-access scheduler that controls the WiFi hardware to access the WiFi communication channel by way of a TDMA channel-access method.

Abstract: A computer-implemented method executed using a first networked computer and comprising: receiving a digitally stored workflow pattern that specifies at least an input data source, a data transformation process, and an output data destination, the workflow pattern comprising a structured plurality of name declarations and value specifications that are human readable and machine readable, the data transformation process specified in the workflow pattern including one or more references to processing logic, a processing logic source outside the workflow pattern at which the processing logic is stored, and one or more available process engines that are capable of processing the processing logic; machine parsing the workflow pattern and dividing the workflow pattern into a plurality of execution units, each execution unit being associated with a particular process engine among the one or more available process engines; accessing the input data source specified in the workflow pattern and loading at least a portion

Abstract: A computer-implemented method executed using a first networked computer and comprising receiving a digitally stored workflow pattern that specifies at least an input data source, a data transformation process, an output data destination, a data quality assertion and a data quality source; the workflow pattern comprising a structured plurality of name declarations and value specifications that are human readable and machine readable; the data transformation process specified in the workflow pattern including one or more references to processing logic, a processing logic source outside the workflow pattern at which the processing logic is stored, and one or more available process engines that are capable of processing the processing logic; machine parsing the workflow pattern and dividing the workflow pattern into a plurality of execution units, each execution unit being associated with a particular process engine among the one or more available process engines; accessing the input data source specified in the

Abstract: A computer-implemented method executed using a first networked computer and comprising: receiving a digitally stored workflow pattern that specifies at least an input data source, a data transformation process, and an output data destination, the workflow pattern comprising a structured plurality of name declarations and value specifications that are human readable and machine readable, the data transformation process specified in the workflow pattern including one or more references to processing logic, a processing logic source outside the workflow pattern at which the processing logic is stored, and one or more available process engines that are capable of processing the processing logic; machine parsing the workflow pattern and dividing the workflow pattern into a plurality of execution units, each execution unit being associated with a particular process engine among the one or more available process engines; accessing the input data source specified in the workflow pattern and loading at least a portion

Abstract: A computer-implemented method executed using a first networked computer and comprising receiving a digitally stored workflow pattern that specifies at least an input data source, a data transformation process, an output data destination, a data quality assertion and a data quality source; the workflow pattern comprising a structured plurality of name declarations and value specifications that are human readable and machine readable; the data transformation process specified in the workflow pattern including one or more references to processing logic, a processing logic source outside the workflow pattern at which the processing logic is stored, and one or more available process engines that are capable of processing the processing logic; machine parsing the workflow pattern and dividing the workflow pattern into a plurality of execution units, each execution unit being associated with a particular process engine among the one or more available process engines; accessing the input data source specified in the

Abstract: The present invention provides a metal-organic framework material for the adsorptive separation of acetylene/ethylene mixture and preparation method therefor. The metal-organic framework material is named TJE-2 with a chemical formula of [Ni(pyc)(apyz)]n, wherein, Ni represents nickel as a metal center, pyc represents the organic ligand 1H-pyrazole-4-carboxylic acid, and apyz represents the organic ligand 2-aminopyrazine. The preparation method is as follows: thoroughly dissolving pyc, apyz and Ni(NO3)2·6H2O, transferring the mixture to a pressure-resistant closed container for heating reaction, followed by solvent exchange and activation to obtain a homogeneous powder material. The ultra-microporous metal-organic framework material prepared by the present invention features a significantly high C2H2 adsorption capacity, good selectivity, and low raw material costs, and therefore can realize C2H2/C2H4 separation at lower costs.

Abstract: Disclosed is a method for continuously producing polyaluminum chloride from aluminum slag, comprising: blending the aluminum slag with water into a slurry in a mixing tank; pumping the slurry and a sodium hydroxide solution into a first mixing reactor; introducing the mixture obtained in the first mixing reactor into a second mixing reactor and pumping hydrochloric acid into the second mixing reactor; and filtering the resulting mixture and allowing filtrate for ripening, polymerization and sedimentation to obtain liquid polyaluminum chloride; wherein each of the reactors is pipeline-shaped, arranged horizontally and provided with a spiral conveyor shaft inside which is arranged horizontally and configured to stir and convey the mixture in a pipeline. This method realizes a continuous treatment of aluminum slag together with a continuous recovery of ammonia nitrogen and produces PAC, thereby achieving resourceful utilization and improved operability.

Abstract: A method, an apparatus and a system for conveniently measuring coronary artery vascular evaluation parameters are provided by the disclosure.

Abstract: An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a not-and (NAND) operation according to the first sampled signal and the second sampled signal to produce an activation signal for activating a frequency adjustment for the clock signal.

Abstract: A reference-less frequency detector circuit includes a sampling circuit that is configured to generate a frequency control voltage and a switch circuit control signal based on a frequency difference between a clock signal frequency and an input data rate. The frequency control voltage has a frequency down indication and a frequency up indication. A voltage-to-current converter circuit is coupled to the sampling circuit and is configured to convert the frequency control voltage to a frequency control current based on the switch circuit control signal. The voltage-to-current converter circuit includes an output switch circuit controlled by the switch control signal and is configured to have substantially equal respective latencies for the frequency down indication and the frequency up indication.

Abstract: A reference-less frequency detector circuit includes a sampling circuit that is configured to generate a frequency control voltage and a switch circuit control signal based on a frequency difference between a clock signal frequency and an input data rate. The frequency control voltage has a frequency down indication and a frequency up indication. A voltage-to-current converter circuit is coupled to the sampling circuit and is configured to convert the frequency control voltage to a frequency control current based on the switch circuit control signal. The voltage-to-current converter circuit includes an output switch circuit controlled by the switch control signal and is configured to have substantially equal respective latencies for the frequency down indication and the frequency up indication.

Abstract: A multiplexer comprises: an output circuit comprising a multiplexer output; and a first buffer coupled to the output circuit and comprising: a first selection input configured to receive a first selection signal; a first logical input configured to receive a first logical input signal; and a first ground; wherein the multiplexer is configured to: couple the first logical input to the multiplexer output when the first selection signal is a first value; and couple the first logical input to the first ground when the first selection signal is a second value. A method comprises: receiving a selection signal and a first logical input signal; coupling a first logical input to a multiplexer output when the selection signal is a first value; and coupling the first logical input to a ground when the selection signal is a second value.

Abstract: An apparatus comprising an input port configured to receive an input signal propagated through a transmission link, wherein the transmission link comprises a low-frequency channel loss and a high-frequency channel loss, a continuous-time linear equalization (CTLE) circuit coupled to the input port and configured to produce an output signal according to the input signal by applying a first gain to the input signal at a first frequency to compensate the low-frequency loss, and applying a second gain to the input signal at a second frequency to compensate the high-frequency channel loss, and an output port coupled to the CTLE circuit and configured to output the output signal.

Abstract: A reference-less frequency detector circuit includes a sampling circuit that is configured to generate a frequency control voltage and a switch circuit control signal based on a frequency difference between a clock signal frequency and an input data rate. The frequency control voltage has a frequency down indication and a frequency up indication. A voltage-to-current converter circuit is coupled to the sampling circuit and is configured to convert the frequency control voltage to a frequency control current based on the switch circuit control signal. The voltage-to-current converter circuit includes an output switch circuit controlled by the switch control signal and is configured to have substantially equal respective latencies for the frequency down indication and the frequency up indication.

Abstract: A reference-less frequency detector circuit includes a sampling circuit that is configured to generate a frequency control voltage and a switch circuit control signal based on a frequency difference between a clock signal frequency and an input data rate. The frequency control voltage has a frequency down indication and a frequency up indication. A voltage-to-current converter circuit is coupled to the sampling circuit and is configured to convert the frequency control voltage to a frequency control current based on the switch circuit control signal. The voltage-to-current converter circuit includes an output switch circuit controlled by the switch control signal and is configured to have substantially equal respective latencies for the frequency down indication and the frequency up indication.

Abstract: An electronic driver circuit for use with a modulator such as a segmented Mach-Zehnder Modulator (MZM) is provided. The electronic driver circuit includes a first delay buffer implemented as a first complementary metal-oxide-semiconductor (CMOS) inverter and a second delay buffer implemented as a second CMOS inverter. The second CMOS inverter follows the first CMOS inverter and has a second gate width smaller than a first gate width of the first CMOS inverter. The first CMOS inverter is configured to produce a first delayed electrical signal from a received electrical signal and the second CMOS inverter is configured to produce a second delayed electrical signal from the first delayed electrical signal produced by the first CMOS inverter.