Patents by Inventor Yi-Fan Li

Yi-Fan Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250240985
    Abstract: The invention provides a semiconductor structure with a deep trench capacitor structures, which comprises a substrate, the substrate comprises a bottle-shaped trench, wherein the bottle-shaped trench has an upper part and a lower part in a cross section, and the interface between the upper part and the lower part is a bottleneck line, wherein the bottleneck line is the part with the smallest width in the bottle-shaped trench, a first dielectric layer is filled in the bottle-shaped trench, and a void is located in the first dielectric layer, wherein the highest point of the void is lower than the bottleneck line.
    Type: Application
    Filed: February 21, 2024
    Publication date: July 24, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Nan-Yuan Huang, Kuan-Jhih Hou, Yu-Fu Wang, Ya-Yin Hsiao, Po-Ching Su, Ti-Bin Chen, Chih-Chiang Wu, Yao-Jhan Wang
  • Publication number: 20250212426
    Abstract: A MIM capacitor structure includes a semiconductor substrate, and a first trench and a second trench in the semiconductor substrate in a capacitance forming region. The second trench is adjacent to the first trench. The second trench is deeper than the first trench. A dielectric liner layer conformally covers a top surface of the semiconductor substrate and interior surfaces of the first trench and the second trench. A bottom electrode layer conformally covers the dielectric liner layer. The bottom electrode layer extends onto a top surface of the semiconductor substrate. A capacitor dielectric layer is disposed on the bottom electrode layer in the first trench and the second trench. A top electrode layer is disposed on the capacitor dielectric layer in the first trench and the second trench. The top surface of the top electrode layer is coplanar with the top surface of the bottom electrode layer.
    Type: Application
    Filed: January 10, 2024
    Publication date: June 26, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tai-Cheng Hou, Da-Jun Lin, Bin-Siang Tsai, Fu-Yu Tsai, Ya-Yin Hsiao, Po-Ching Su, Yi-Fan Li, Kuan-Jhih Hou, Yu-Fu Wang, Ti-Bin Chen, Chih-Chiang Wu, Yao-Jhan Wang
  • Publication number: 20250159964
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.
    Type: Application
    Filed: January 15, 2025
    Publication date: May 15, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih-Chiang Wu, Ti-Bin Chen
  • Publication number: 20250089334
    Abstract: A semiconductor includes a substrate. A gate structure is disposed on the substrate. A liner oxide contacts a side of the gate structure. A silicon oxide spacer contacts the liner oxide. An end of the silicon oxide spacer forms a kink profile. A silicon nitride spacer contacts the silicon oxide spacer and a tail of the silicon nitride spacer covers part of the kink profile. A stressor covers the silicon nitride spacer and the substrate.
    Type: Application
    Filed: October 13, 2023
    Publication date: March 13, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Chen-Ming Wang, Po-Ching Su, Pei-Hsun Kao, Ti-Bin Chen, Chun-Wei Yu, Chih-Chiang Wu
  • Patent number: 12237394
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: February 25, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih-Chiang Wu, Ti-Bin Chen
  • Publication number: 20250015158
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.
    Type: Application
    Filed: September 18, 2024
    Publication date: January 9, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih-Chiang Wu, Ti-Bin Chen
  • Patent number: 12125890
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: October 22, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih-Chiang Wu, Ti-Bin Chen
  • Publication number: 20240332087
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.
    Type: Application
    Filed: June 10, 2024
    Publication date: October 3, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Po-Ching Su, Yu-Fu Wang, Min-Hua Tsai, Ti-Bin Chen, Chih-Chiang Wu, Tzu-Chin Wu
  • Publication number: 20240332086
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.
    Type: Application
    Filed: June 10, 2024
    Publication date: October 3, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Po-Ching Su, Yu-Fu Wang, Min-Hua Tsai, Ti-Bin Chen, Chih-Chiang Wu, Tzu-Chin Wu
  • Publication number: 20240274715
    Abstract: A semiconductor device includes a gate structure on a substrate and an epitaxial layer adjacent to the gate structure, in which the epitaxial layer includes a first buffer layer, an anisotropic layer on the first buffer layer, a second buffer layer on the first buffer layer, and a bulk layer on the anisotropic layer. Preferably, a concentration of boron in the bulk layer is less than a concentration of boron in the anisotropic layer, a concentration of boron in the first buffer layer is less than a concentration of boron in the second buffer layer, and the concentration of boron in the second buffer layer is less than the concentration of boron in the anisotropic layer.
    Type: Application
    Filed: March 21, 2023
    Publication date: August 15, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Hsiang Wang, Yi-Fan Li, Chung-Ting Huang, Chi-Hsuan Tang, Chun-Jen Chen, Ti-Bin Chen, Chih-Chiang Wu
  • Patent number: 12040234
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: July 16, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Po-Ching Su, Yu-Fu Wang, Min-Hua Tsai, Ti-Bin Chen, Chih-Chiang Wu, Tzu-Chin Wu
  • Publication number: 20230369442
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih- Chiang Wu, Ti-Bin Chen
  • Publication number: 20230369441
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih-Chiang Wu, Ti-Bin Chen
  • Patent number: 11757016
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: September 12, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih-Chiang Wu, Ti-Bin Chen
  • Patent number: 11705492
    Abstract: A first gate and a second gate are formed on a substrate with a gap between the first and second gates. The first gate has a first sidewall. The second gate has a second sidewall directly facing the first sidewall. A first sidewall spacer is disposed on the first sidewall. A second sidewall spacer is disposed on the second sidewall. A contact etch stop layer is deposited on the first and second gates and on the first and second sidewall spacers. The contact etch stop layer is subjected to a tilt-angle plasma etching process to trim a corner portion of the contact etch stop layer. An inter-layer dielectric layer is then deposited on the contact etch stop layer and into the gap.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: July 18, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Kuo-Chin Hung, Wen-Yi Teng, Ti-Bin Chen
  • Publication number: 20230005795
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.
    Type: Application
    Filed: August 3, 2021
    Publication date: January 5, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Po-Ching Su, Yu-Fu Wang, Min-Hua Tsai, Ti-Bin Chen, Chih-Chiang Wu, Tzu-Chin Wu
  • Publication number: 20220223710
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.
    Type: Application
    Filed: March 30, 2022
    Publication date: July 14, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih-Chiang Wu, Ti-Bin Chen
  • Patent number: 11322598
    Abstract: A semiconductor device includes a substrate having a first region and a second region and a gate structure on the first region and the second region of the substrate. The gate structure includes a first bottom barrier metal (BBM) layer on the first region and the second region, a first work function metal (WFM) layer on the first region; and a diffusion barrier layer on a top surface and a sidewall of the first WFM layer on the first region and the first BBM layer on the second region. Preferably, a thickness of the first BBM layer on the second region is less than a thickness of the first BBM layer on the first region.
    Type: Grant
    Filed: June 21, 2020
    Date of Patent: May 3, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: YI-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih-Chiang Wu, Ti-Bin Chen
  • Publication number: 20210257471
    Abstract: A first gate and a second gate are formed on a substrate with a gap between the first and second gates. The first gate has a first sidewall. The second gate has a second sidewall directly facing the first sidewall. A first sidewall spacer is disposed on the first sidewall. A second sidewall spacer is disposed on the second sidewall. A contact etch stop layer is deposited on the first and second gates and on the first and second sidewall spacers. The contact etch stop layer is subjected to a tilt-angle plasma etching process to trim a corner portion of the contact etch stop layer. An inter-layer dielectric layer is then deposited on the contact etch stop layer and into the gap.
    Type: Application
    Filed: May 3, 2021
    Publication date: August 19, 2021
    Inventors: Yi-Fan Li, Kuo-Chin Hung, Wen-Yi Teng, Ti-Bin Chen
  • Patent number: 11031477
    Abstract: A first dummy gate and a second dummy gate are formed on a substrate with a gap between the first and second dummy gates. The first dummy gate has a first sidewall. The second dummy gate has a second sidewall directly facing the first sidewall. A first sidewall spacer is disposed on the first sidewall. A second sidewall spacer is disposed on the second sidewall. A contact etch stop layer is deposited on the first and second dummy gates and on the first and second sidewall spacers. The contact etch stop layer is subjected to a tilt-angle plasma etching process to trim a corner portion of the contact etch stop layer. An inter-layer dielectric layer is then deposited on the contact etch stop layer and into the gap.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: June 8, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Kuo-Chin Hung, Wen-Yi Teng, Ti-Bin Chen