Abstract: Methods, apparatus, and computer programs are disclosed to schedule access to multiple accelerators. In one embodiment, a method is disclosed to perform: receiving a first request to process data for a first application by a first accelerator of a plurality of accelerators of a computing system, an accelerator of the plurality of accelerators being dedicated to one or more respective specialized computations of the computing system for data processing; scheduling resources for the first request based on the first request and a second request to process data for a second application by a second accelerator of the plurality of accelerators, the first and second requests having one or more priority indications indicating priority between the first and second requests; and processing the data for the first application using the resources as scheduled responsive to the first request.

Abstract: A method for batching pages for a data movement accelerator of a processor. The method includes determining a plurality of memory regions having a similar content according to a similarity criterion, wherein each memory region comprises a plurality of pages. The method further includes determining a plurality of page groups, wherein each page group comprises a plurality of counterpart pages between the plurality of memory regions. The method then includes providing the plurality of page groups to the data movement accelerator for parallel processing.

Abstract: Methods and apparatus for efficiently merging non-identical pages in Kernel Same-page Merging (KSM) for efficient and improved memory deduplication and security. The methods and apparatus identify memory pages with similar data and selectively merge those pages based on criteria such as a threshold. Memory pages in memory for a computing platform are scanned to identify pages storing similar but not identical data. A delta record between the similar memory pages is created, and it is determined whether a size of the delta (i.e., amount of content that is different) is less than a threshold. If so, the delta record is used to merge the pages. In one aspect, operations for creating delta records and merging the content of memory pages using delta records is offloaded from a platform's CPU. Support for memory reads and memory writes are provided utilizing delta records, including merging and unmerging pages under applicable conditions.

Abstract: Examples described herein relates to a network interface apparatus that includes packet processing circuitry and a bus interface. In some examples, the packet processing circuitry to: process a received packet that includes data, a request to perform a write operation to write the data to a cache, and an indicator that the data is to be durable and based at least on the received packet including the request and the indicator, cause the data to be written to the cache and non-volatile memory. In some examples, the packet processing circuitry is to issue a command to an input output (IO) controller to cause the IO controller to write the data to the cache and the non-volatile memory.

Abstract: A central processing unit can offload table lookup or tree traversal to an offload engine. The offload engine can provide hardware accelerated operations such as instruction queueing, bit masking, hashing functions, data comparisons, a results queue, and a progress tracking. The offload engine can be associated with a last level cache. In the case of a hash table lookup, the offload engine can apply a hashing function to a key to generate a signature, apply a comparator to compare signatures against the generated signature, retrieve a key associated with the signature, and apply the comparator to compare the key against the retrieved key. Accordingly, a data pointer associated with the key can be provided in the result queue. Acceleration of operations in tree traversal and tuple search can also occur.

Abstract: The present disclosure provides a method for strength measurement, including: obtaining action information at one or more rounds corresponding to one or more rounds of test actions completed by a user to be tested on a strength-type intelligent fitness device; and updating a measurement parameter of the strength-type intelligent fitness device based on the action information at the one or more rounds. The method further comprises determining a next round of a test action based on the updated measurement parameter; and calculating and obtaining maximum strength information of the user to be tested based on the action information during N rounds of the test actions.

Abstract: Examples described herein relates to a network interface apparatus that includes packet processing circuitry and a bus interface. In some examples, the packet processing circuitry to: process a received packet that includes data, a request to perform a write operation to write the data to a cache, and an indicator that the data is to be durable and based at least on the received packet including the request and the indicator, cause the data to be written to the cache and non-volatile memory. In some examples, the packet processing circuitry is to issue a command to an input output (IO) controller to cause the IO controller to write the data to the cache and the non-volatile memory.

Abstract: Examples described herein relate to a work scheduler that includes at least one processor and at least one queue. In some examples, the work scheduler receives a request to allocate a region of memory and based on availability of a memory segment associated with a central cache to satisfy the request to allocate a region of memory, provide a memory allocation using an available memory segment entry associated with the central cache from the at least one queue. In some examples, the work scheduler assigns a workload to a processor and controls when to pre-fetch content relevant to the workload to store in a cache or memory accessible to the processor based on a position of the workload in a work queue associated with the processor.

Abstract: A central processing unit can offload table lookup or tree traversal to an offload engine. The offload engine can provide hardware accelerated operations such as instruction queueing, bit masking, hashing functions, data comparisons, a results queue, and a progress tracking. The offload engine can be associated with a last level cache. In the case of a hash table lookup, the offload engine can apply a hashing function to a key to generate a signature, apply a comparator to compare signatures against the generated signature, retrieve a key associated with the signature, and apply the comparator to compare the key against the retrieved key. Accordingly, a data pointer associated with the key can be provided in the result queue. Acceleration of operations in tree traversal and tuple search can also occur.