Abstract: An electronic device comprises a stack of alternating dielectric materials and conductive materials, a pillar region extending vertically through the stack, an oxide material within the pillar region and laterally adjacent to the dielectric materials and the conductive materials of the stack, and a storage node laterally adjacent to the oxide material and within the pillar region. A charge confinement region of the storage node is in horizontal alignment with the conductive materials of the stack. A height of the charge confinement region in a vertical direction is less than a height of a respective, laterally adjacent conductive material of the stack in the vertical direction. Related methods and systems are also disclosed.

Abstract: An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.

Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: A microelectronic device comprises conductive structures and insulative structures vertically alternating with the conductive structures. At least one of the insulative structures includes interfacial regions extending inward from vertical boundaries of the at least one of the insulative structures, and central region vertically interposed between the interfacial regions. The interfacial regions are doped with one or more of carbon and boron. The insulative structures comprise a lower concentration of the one or more of carbon and boron than the interfacial regions. Additional microelectronic devices, electronic systems, and methods are also described.

Abstract: An electronic device includes a stack structure including vertically alternating dielectric materials and conductive materials, the conductive materials including first regions and second regions, and pillars extending vertically through the stack structure, the pillars adjacent to the second regions of the conductive materials. The pillars include cell films adjacent to the second regions, the cell films including a high-k dielectric material, a barrier oxide material, a storage node material, a tunneling material, and a channel material. Segments of each of the high-k dielectric material, the barrier oxide material, and the storage node material are adjacent to the second regions. A length of the segments of high-k dielectric material and a length of the segments of storage node material adjacent to the second regions are greater than a height of the first regions of the conductive materials. Related methods and systems are also disclosed.

Abstract: Methods and apparatuses associated with rebooting a computing device are described. Examples can include receiving at a processing resource of a computing device first signaling associated with boot programs of the computing device and second signaling associated with a boot sequence of the computing device. Examples can include writing from the processing resource to a memory resource data that is based at least in part on the first and the second signaling and writing from the processing resource to the memory resource data representative of activity of the computing device. Examples can include identifying data representative of a boot process for the computing device and rebooting the computing device in a particular sequence including the monitored activity, based at least in part on the data representative of the boot process responsive to a shutdown, restart, or both, of the computing device.

Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: A multi-rotor unmanned aerial vehicle (UAV) comprises: a fuselage; a plurality of rotor mechanisms disposed on the fuselage, each rotor mechanism including a rotor; and a plurality of connection mechanisms disposed on the fuselage. The plurality of connection mechanisms have a one-to-one correspondence with the plurality of rotor mechanisms, each connection mechanism corresponding to one of the plurality of rotor mechanisms. Each rotor mechanism is movably connected to the fuselage through the corresponding connection mechanism; and the plurality of rotor mechanisms are configured to be rotated with respect to the corresponding connection mechanisms to cause the plurality of rotor mechanisms to overlap with each other and form a rotor mechanism assembly.

Abstract: Methods and apparatuses associated with rebooting a computing device are described. Examples can include receiving at a processing resource of a computing device first signaling associated with boot programs of the computing device and second signaling associated with a boot sequence of the computing device. Examples can include writing from the processing resource to a memory resource data that is based at least in part on the first and the second signaling and writing from the processing resource to the memory resource data representative of activity of the computing device. Examples can include identifying data representative of a boot process for the computing device and rebooting the computing device in a particular sequence including the monitored activity, based at least in part on the data representative of the boot process responsive to a shutdown, restart, or both, of the computing device.

Abstract: A gimbal photographing device includes a body including a supporting wall and a side wall adjacent to the supporting wall, a folding mechanism connected to the body and configured to rotate around a rotation axis, and a gimbal camera connected to the folding mechanism and having an expanded state and a folded state. In response to the folding mechanism driving the gimbal camera to rotate to the expanded state, at least a portion of the folding mechanism abuts against the supporting wall. In response to the folding mechanism driving the gimbal camera to rotate to the folded state, the gimbal camera fits to the side wall of the body.

Abstract: An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.

Abstract: An electronic device comprising first blocks and second blocks of an array comprising memory cells. The memory cells in the first and second blocks comprise memory pillars extending through a stack. The memory pillars comprise a charge blocking material laterally adjacent to the stack, a storage nitride material laterally adjacent to the charge blocking material, a tunnel dielectric material laterally adjacent to the storage nitride material, a channel material laterally adjacent to the tunnel dielectric material, and a fill material between opposing sides of the channel material. One or more of the storage nitride material and the tunnel dielectric material in the first blocks differ in thickness or in material composition from one or more of the storage nitride material and the tunnel dielectric material in the second blocks. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

Abstract: Methods and apparatuses associated with rebooting a computing device are described. Examples can include receiving at a processing resource of a computing device first signaling associated with boot programs of the computing device and second signaling associated with a boot sequence of the computing device. Examples can include writing from the processing resource to a memory resource data that is based at least in part on the first and the second signaling and writing from the processing resource to the memory resource data representative of activity of the computing device. Examples can include identifying data representative of a boot process for the computing device and rebooting the computing device in a particular sequence including the monitored activity, based at least in part on the data representative of the boot process responsive to a shutdown, restart, or both, of the computing device.

Abstract: An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.

Abstract: A gimbal assembly includes a body and a gimbal frame movably connected with the body. The gimbal frame is configured to completely fit with the body or partially fit with the body through a sliding mechanism to reduce a volume of the gimbal assembly. The sliding mechanism includes a first sliding member disposed at the body and a second sliding member disposed at the gimbal frame to match with the first sliding member, such that the gimbal frame slides from an extended position to a receiving position with respect to the body.

Abstract: Methods and non-transitory machine-readable media associated with clothing recommendations are described. Clothing recommendations can include identifying, using a model built based on input data previously received in association with an article of clothing associated with a child, physical data associated with the child, and image data of the child with a reference object, output data representative of a clothing size recommendation for the child and sending, in response to a user request or a data refresh, the clothing size recommendation, a different article of clothing recommendation for the child based at least in part on the output data, or both, to a user device.

Abstract: Methods and apparatuses associated with rebooting a computing device are described. Examples can include receiving at a processing resource of a computing device first signaling associated with boot programs of the computing device and second signaling associated with a boot sequence of the computing device. Examples can include writing from the processing resource to a memory resource data that is based at least in part on the first and the second signaling and writing from the processing resource to the memory resource data representative of activity of the computing device. Examples can include identifying data representative of a boot process for the computing device and rebooting the computing device in a particular sequence including the monitored activity, based at least in part on the data representative of the boot process responsive to a shutdown, restart, or both, of the computing device.

Abstract: An electronic device comprises a stack of alternating dielectric materials and conductive materials, a pillar region extending vertically through the stack, an oxide material within the pillar region and laterally adjacent to the dielectric materials and the conductive materials of the stack, and a storage node laterally adjacent to the oxide material and within the pillar region. A charge confinement region of the storage node is in horizontal alignment with the conductive materials of the stack. A height of the charge confinement region in a vertical direction is less than a height of a respective, laterally adjacent conductive material of the stack in the vertical direction. Related methods and systems are also disclosed.

Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.