Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.

Abstract: An information handling system with modular riser components for receiving expansion cards having various requirements. The system includes a riser body assembly having a common support structure for receiving expansion cards. The common support structure may be coupled to different expansion structures to provide support of expansion cards having requirements that would not be met by the common support structure alone.

Abstract: A reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (MTJ). A control circuit is coupled to a first terminal of the at least one MTJ and is configured to selectively flow current through the at least one MTJ in the forward and inverse direction to generate a reference current.

Abstract: A semiconductor package includes a die stack including a first semiconductor die having a first interconnect structure, and a second semiconductor die having a second interconnect structure direct bonding to the first interconnect structure of the first semiconductor die. The second interconnect structure includes connecting pads disposed in a peripheral region around the first semiconductor die. First connecting elements are disposed on the connecting pads, respectively. A substrate includes second connecting elements on a mounting surface of the substrate. The first connecting elements are electrically connected to the second connecting elements through an anisotropic conductive structure.

Abstract: The present disclosure relates to a semiconductor package, a semiconductor bonding structure and a method of fabricating the same. The semiconductor package includes a first chip, a second chip and a conductive structure, wherein the conductive structure is disposed at a side of the second chip and over a second upper surface of the first interconnection structure to electrically connect to the first interconnection structure. The semiconductor bonding structure includes a first substrate, a plurality of first interconnection structures, a plurality of chips and a plurality of conductive structures, wherein the conductive structures are respectively disposed at a side of each of the chips and over a second upper surface of each first interconnection structure, to electrically connect to each first interconnection.

Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.

Abstract: A gas detection and cleaning system for a vehicle is disclosed and includes an external modular base, a gas detection module and a cleaning device. The gas detection module is connected to a first external connection port of the external modular base to detect a gas in the vehicle and output the information datum. The information datum is transmitted through the first external connection port to a driving and controlling module of the external modular base, processed and converted into an actuation information datum for being externally outputted through a second external connection port of the external modular base. The cleaning device is connected with the second external connection port through an external port to receive the actuation information datum outputted from the second external connection port to actuate or close the cleaning device.

Abstract: A semiconductor device, including a substrate, a first source/drain region, a second source/drain region, and a gate structure, is provided. The substrate has an extra body portion and a fin protruding from a top surface of the substrate, wherein the fin spans the extra body portion. The first source/drain region and the second source/drain region are in the fin. The gate structure spans the fin, is located above the extra body portion, and is located between the first source/drain region and the second source/drain region.

Abstract: An integrated circuit is provided. The integrated circuit includes a three-dimensional memory device, a first word line driving circuit and a second word line driving circuit. The three-dimensional memory device includes stacking structures separately extending along a column direction. Each stacking structure includes a stack of word lines. The stacking structures have first staircase structures at a first side and second staircase structures at a second side. The word lines extend to steps of the first and second staircase structures. The first and second word line driving circuits lie below the three-dimensional memory device, and extend along the first and second sides, respectively. Some of the word lines in each stacking structure are routed to the first word line driving circuit from a first staircase structure, and others of the word lines in each stacking structure are routed to the second word line driving circuit from a second staircase structure.

Abstract: A semiconductor device comprises a first semiconductor structure, a second semiconductor structure located on the first semiconductor structure, and an active layer located between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure has a first conductivity type, and includes a plurality of first layers and a plurality of second layers alternately stacked. The second semiconductor structure has a second conductivity type opposite to the first conductivity type. The plurality of first layers and the plurality of second layers include indium and phosphorus, and the plurality of first layers and the plurality of second layers respectively have a first indium atomic percentage and a second indium atomic percentage. The second indium atomic percentage is different from the first indium atomic percentage.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A resonant converter having a pre-conduction mechanism for realizing a wide output voltage range is provided. The resonant converter includes a first circuit and a second circuit. The first circuit includes a plurality of primary-side switches. The plurality of primary-side switches includes a first high-side switch, a second high-side switch, a first low-side switch and a second low-side switch. The second circuit includes a plurality of secondary-side switches. The plurality of secondary-side switches includes a third high-side switch, a fourth high-side switch, a third low-side switch and a fourth low-side switch. When the second low-side switch and the first low-side switch are turned on and a current time reaches a preset on time, the fourth high-side switch and the third low-side switch are turned on.

Abstract: In example implementations, an apparatus is provided. The apparatus includes an interface, a previous generation carrier connected to the interface, a controller communicatively coupled to the interface, and a basic input/output system (BIOS). The previous generation carrier includes a current generation memory card. The controller is to detect the previous generation carrier. The BIOS is to set the interface to operate at a speed associated with the previous generation carrier in response to detection of the previous generation carrier.

Abstract: In example implementations, an apparatus is provided. The apparatus includes a polymer based enclosure, an absorber, and a connection interface. The polymer based enclosure is shaped to enclose a memory module connected to a memory module connection interface on a printed circuit board. The absorber is coated over the polymer based enclosure to block radio frequency signals generated by the memory modules. The connection interface is to connect to the memory module connection interface.

Abstract: A resonant converter having a pre-conduction mechanism for realizing a wide output voltage range is provided. The resonant converter includes a first circuit and a second circuit. The first circuit includes a plurality of primary-side switches. The plurality of primary-side switches includes a first high-side switch, a second high-side switch, a first low-side switch and a second low-side switch. The second circuit includes a plurality of secondary-side switches. The plurality of secondary-side switches includes a third high-side switch, a fourth high-side switch, a third low-side switch and a fourth low-side switch. When the second low-side switch and the first low-side switch are turned on and a current time reaches a preset on time, the fourth high-side switch and the third low-side switch are turned on.

Abstract: An interleaved three-phase Y-Delta connected power converter is provided. The interleaved three-phase Y-Delta connected power converter includes an input voltage source, an input capacitor, a first converter module, a second converter module, an output circuit, and a control circuit. The control circuit calculates a phase shift amount and an operating frequency through voltage and current feedbacks to generate a plurality of switch signal groups for controlling the first converter module and the second converter module, respectively.

Abstract: The present invention provides a server including a SSD, a first node and a second node, wherein the first node comprises a first processor and a first memory, and the second node comprises a second processor and a second memory. When the first processor receives data from another device via network, the first processor stores the data in the first memory, and the first processor further sends the data to the second node; when the second processor receives the data from the first node, the second processor stores the data in the second memory, and the second processor further sends a notification to the first node to inform that the data is successfully stored in the second memory; and after and only after the first processor receives the notification from the second node, the first processor starts to write the data into the SSD.

Abstract: An interleaved three-phase Y-Delta connected power converter is provided. The interleaved three-phase Y-Delta connected power converter includes an input voltage source, an input capacitor, a first converter module, a second converter module, an output circuit, and a control circuit. The control circuit calculates a phase shift amount and an operating frequency through voltage and current feedbacks to generate a plurality of switch signal groups for controlling the first converter module and the second converter module, respectively.