Abstract: A network processor includes a plurality of processing cores configured to process data packets, and a processing mode mechanism configurable to configure the processing cores between a pipeline processing mode and a parallel processing mode. The processing mode mechanism may include switch elements, or a fabric logic and a bus, configurable to interconnect the processing cores to operate in either the pipeline processing mode or the parallel processing mode.

Abstract: A network element is configured to store a plurality of flow table entries each having first and second portions, wherein the first portion can be read only and the second portion can be read and modified. The network element includes a first memory configured to store the first portion of the flow table entries and a second memory configured to store the second portion of the flow table entries. A plurality of processing cores are configured to process data packets in accordance with the flow table entries, each of the processing cores being further configured to access the first portion of the flow table entries in the first memory. A module is configured to exclusively access the second portion of the flow table entries in the second memory to support the processing of the data packets by the processing cores.

Abstract: A network processor includes a plurality of processing cores configured to process data packets, and a processing mode mechanism configurable to configure the processing cores between a pipeline processing mode and a parallel processing mode. The processing mode mechanism may include switch elements, or a fabric logic and a bus, configurable to interconnect the processing cores to operate in either the pipeline processing mode or the parallel processing mode.