Patents by Inventor Yifeng W. Yan

Yifeng W. Yan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6784478
    Abstract: An apparatus and fabrication process for a capacitor formed in conjunction with a dual damascene process. A bottom capacitor plate is electrically connected to an overlying first conductive via formed according to the dual damascene process. A top capacitor plate is connected to an overlying second conductive via. A dielectric material is disposed between the top and the bottom plates. The capacitor is formed by successively forming the bottom plate, the dielectric layer, and the top plate, patterning these layers as required after their formation. The first conductive via is formed over and electrically connected to the bottom plate and the second conductive via is formed over and connected to the top capacitor plate thereby providing for interconnection of the capacitor to other circuit elements by way of the dual damascene conductive runners connected to the conductive vias.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: August 31, 2004
    Assignee: Agere Systems Inc.
    Inventors: Sailesh M. Merchant, Yifeng W. Yan
  • Publication number: 20040061177
    Abstract: An apparatus and fabrication process for a capacitor formed in conjunction with a dual damascene process. A bottom capacitor plate is electrically connected to an overlying first conductive via formed according to the dual damascene process. A top capacitor plate is connected to an overlying second conductive via. A dielectric material is disposed between the top and the bottom plates. The capacitor is formed by successively forming the bottom plate, the dielectric layer, and the top plate, patterning these layers as required after their formation. The first conductive via is formed over and electrically connected to the bottom plate and the second conductive via is formed over and connected to the top capacitor plate thereby providing for interconnection of the capacitor to other circuit elements by way of the dual damascene conductive runners connected to the conductive vias.
    Type: Application
    Filed: September 30, 2002
    Publication date: April 1, 2004
    Inventors: Sailesh M. Merchant, Yifeng W. Yan
  • Patent number: 6288648
    Abstract: The present invention provides a method of manufacturing an integrated circuit using a conditioning wheel status indicator with a polishing apparatus having a conditioning wheel and a polishing pad. In one embodiment, the conditioning wheel status indicator comprises a drive motor, an ammeter, and an indicator. The drive motor is coupled to the conditioning wheel and configured to rotate the conditioning wheel against the polishing pad at a prescribed rotation rate. The ammeter is coupled to the drive motor and configured to measure a current of the drive motor. The current registered is a nominal current when the conditioning wheel is new. The indicator is coupled to the ammeter and configured to register an excess current that exceeds the nominal current when the conditioning wheel has incurred an undesirable degree of wear.
    Type: Grant
    Filed: August 27, 1999
    Date of Patent: September 11, 2001
    Assignee: Lucent Technologies Inc.
    Inventors: William G. Easter, John A. Maze, Frank Miceli, Yifeng W. Yan