Abstract: A gate driving circuit includes: a pull-up signal output end connected to an input end of a charging circuitry in a shift register unit and configured to apply a pull-up signal to the shift register unit; a pull-down signal output end connected to an input end of a resetting circuitry in the shift register unit and configured to apply a pull-down signal to the shift register unit; and a current detection circuitry connected to the pull-up signal output end and configured to detect a current value outputted by the pull-up signal output end, and/or connected to the pull-down signal output end and configured to detect a current value outputted by the pull-down signal output end. The pull-up signal output end is further configured to output the pull-up signal adjusted in accordance with the current value detected by the current detection circuitry.

Abstract: A gate driver circuit, a display device and a driving method. The gate driver circuit includes: a scan signal generation circuit, wherein the scan signal generation circuit includes N1 stages of first output terminals, and the scan signal generation circuit is configured to output N1 first pulse scan signals stage by stage respectively through the N1 stages of first output terminals; and N2 level conversion circuits, wherein the N2 level conversion circuits are configured to output under a control of a plurality of conversion control signals N1 second pulse scan signals which are in one-to-one correspondence with the N1 first pulse scan signals, and the plurality of conversion control signals include a plurality of first sub-control signals which are the N1 first pulse scan signals, wherein N1 is an integer greater than or equal to 2, and N2 is an integer greater than or equal to 2.

Abstract: A gate driving unit circuit comprises an input sub-circuit and an output sub-circuit. The input sub-circuit is connected to a first pull-up node, a second pull-up node, and an input terminal, and transmits a signal input from the input terminal to the first pull-up node and the second pull-up node. The output sub-circuit is connected to the first pull-up node, the second pull-up node, a first control terminal, a third control terminal, a first output terminal, and a second output terminal. The output sub-circuit transmits a signal input through the first control terminal to the first output terminal, and transmits a signal input through the third control terminal to the second output terminal under the control of a potential of the second pull-up node, wherein, an effective voltage of a signal of the first control terminal is greater than that of a signal of the third control terminal.

Abstract: A shift register unit and a driving method thereof, a gate drive circuit, and a display device are provided. The shift register unit includes: an input circuit configured to control a potential of a first node; a first output circuit configured to output a carry signal to a first output terminal of the shift register unit through an output terminal of the first output circuit, under control of the potential and a clock signal; a second output circuit configured to output a driving signal to a second output terminal of the shift register unit, under control of the potential and the clock signal; a switching circuit configured to control the output terminal to be electrically connected to the first output terminal in response to a control signal; and a potential control circuit configured to control the output terminal to be electrically connected to a first voltage terminal.

Abstract: A shift register unit, a gate drive circuit, a display device and a method of driving a gate drive circuit are provided. The shift register unit includes a shift register circuit and an output control circuit. The shift register circuit is configured to output a valid output level at a first output terminal according to a first input signal received by a first input terminal, and is configured to reset according to a first reset signal received by a first reset terminal. The output control circuit is configured to output an invalid output level at the second output terminal according to a second input signal received by the second input terminal, thereby controlling a level of the first output terminal to the invalid output level, and is configured to reset according to a second reset signal received by the second reset terminal.

Abstract: A shift register unit, a method of driving a shift register unit, a gate drive circuit, and a display device are provided. The shift register unit includes an input circuit, an output circuit, a first reset circuit, and a reset control circuit. The input circuit is configured to control a level of a first node; the output circuit is configured to output a clock signal to an output terminal; the first reset circuit is configured to reset the first node; and the reset control circuit is configured to input the first reset signal to the first reset circuit in response to a reset control signal and a reference signal, to turn on the first reset circuit and the reset control circuit is further configured to enable an amplitude of a level of the first reset signal to be larger than an amplitude of a level of the reference signal.

Abstract: The present disclose is related to a gate drive unit. The gate drive unit may include a shift register; and a signal filter. The signal filter may respectively connect to a clock signal terminal, a filter output terminal, an input terminal and a reset terminal. The signal filter may be configured, under control of an effective signal provided by the input terminal, to transmit a clock signal of the clock signal terminal to the filter output terminal after the input terminal stops providing the effective signal and before the reset terminal provides an effective signal and, under control of an effective signal provided by the reset terminal, to disconnect the clock signal terminal and the filter output terminal.

Abstract: A gate driver circuit, a display device and a driving method. The gate driver circuit includes: a scan signal generation circuit, wherein the scan signal generation circuit includes N1 stages of first output terminals, and the scan signal generation circuit is configured to output N1 first pulse scan signals stage by stage respectively through the N1 stages of first output terminals; and N2 level conversion circuits, wherein the N2 level conversion circuits are configured to output under a control of a plurality of conversion control signals N1 second pulse scan signals which are in one-to-one correspondence with the N1 first pulse scan signals, and the plurality of conversion control signals include a plurality of first sub-control signals which are the N1 first pulse scan signals, wherein N1 is an integer greater than or equal to 2, and N2 is an integer greater than or equal to 2.

Abstract: A gate driving unit circuit comprises an input sub-circuit and an output sub-circuit. The input sub-circuit is connected to a first pull-up node, a second pull-up node, and an input terminal, and transmits a signal input from the input terminal to the first pull-up node and the second pull-up node. The output sub-circuit is connected to the first pull-up node, the second pull-up node, a first control terminal, a third control terminal, a first output terminal, and a second output terminal. The output sub-circuit transmits a signal input through the first control terminal to the first output terminal, and transmits a signal input through the third control terminal to the second output terminal under the control of a potential of the second pull-up node, wherein, an effective voltage of a signal of the first control terminal is greater than that of a signal of the third control terminal.

Abstract: A shift register unit, a gate driving circuit and a display device are provided. The shift register unit includes a bias control circuit. The bias control circuit is electrically connected to a pull-down node, a control clock signal terminal, and a bias voltage terminal, respectively, and is configured to control connection between the pull-down node and the bias voltage terminal under the control of a control clock signal provided by the control clock signal terminal; and the bias voltage terminal is configured to input a bias voltage signal.

Abstract: A shift register unit, a gate drive circuit, a display device and a method of driving a gate drive circuit are provided. The shift register unit includes a shift register circuit and an output control circuit. The shift register circuit is configured to output a valid output level at a first output terminal according to a first input signal received by a first input terminal, and is configured to reset according to a first reset signal received by a first reset terminal. The output control circuit is configured to output an invalid output level at the second output terminal according to a second input signal received by the second input terminal, thereby controlling a level of the first output terminal to the invalid output level, and is configured to reset according to a second reset signal received by the second reset terminal.

Abstract: A shift register unit, a method of driving a shift register unit, a gate drive circuit, and a display device are provided. The shift register unit includes an input circuit, an output circuit, a first reset circuit, and a reset control circuit. The input circuit is configured to control a level of a first node; the output circuit is configured to output a clock signal to an output terminal; the first reset circuit is configured to reset the first node; and the reset control circuit is configured to input the first reset signal to the first reset circuit in response to a reset control signal and a reference signal, to turn on the first reset circuit and the reset control circuit is further configured to enable an amplitude of a level of the first reset signal to be larger than an amplitude of a level of the reference signal.

Abstract: The present disclosure provides to a shift register unit, a driving method, a gate driving circuit, and a display panel. The shift register unit includes: first and second signal terminals respectively outputting high and low levels alternately, a level logic of a signal output from the second signal terminal being opposite to that from the first signal terminal; first and second pull-down control circuits; a first pull-down circuit coupled to the first pull-down node, the first signal terminal, and a pull-down target node, and transmitting, in response to a signal of the first pull-down node, the signal of the first signal terminal to the pull-down target node; a second pull-down circuit coupled to the second pull-down node, the second signal terminal, and the pull-down target node, and transmitting, in response to a signal of the second pull-down node, the signal of the second signal terminal to the pull-down target node.

Abstract: The present disclosure provides a shift register and a method for driving the same, a gate driving circuit, and a display apparatus. The shift register includes: a node control sub-circuit configured to control a potential at a pull-up node under control of a signal input terminal and a reset terminal; an output sub-circuit configured to provide an output signal to a signal output terminal based on a signal at a clock signal terminal under control of the pull-up node; and at least one gating sub-circuit connected to at least one de-noising node respectively, and each configured to de-noise a respective de-noising node connected thereto independently of the potential at the pull-up node under control of a trigger signal terminal, wherein the at least one de-noising node includes at least one of the pull-up node and the signal output terminal.

Abstract: The present disclose is related to a gate drive unit. The gate drive unit may include a shift register; and a signal filter. The signal filter may respectively connect to a clock signal terminal, a filter output terminal, an input terminal and a reset terminal. The signal filter may be configured, under control of an effective signal provided by the input terminal, to transmit a clock signal of the clock signal terminal to the filter output terminal after the input terminal stops providing the effective signal and before the reset terminal provides an effective signal and, under control of an effective signal provided by the reset terminal, to disconnect the clock signal terminal and the filter output terminal.

Abstract: The present disclosure provides to a shift register unit, a driving method, a gate driving circuit, and a display panel. The shift register unit includes: first and second signal terminals respectively outputting high and low levels alternately, a level logic of a signal output from the second signal terminal being opposite to that from the first signal terminal; first and second pull-down control circuits; a first pull-down circuit coupled to the first pull-down node, the first signal terminal, and a pull-down target node, and transmitting, in response to a signal of the first pull-down node, the signal of the first signal terminal to the pull-down target node; a second pull-down circuit coupled to the second pull-down node, the second signal terminal, and the pull-down target node, and transmitting, in response to a signal of the second pull-down node, the signal of the second signal terminal to the pull-down target node.

Abstract: A shift register unit including a first output circuit configured to transfer a clock signal at a clock signal terminal to a signal output terminal as an output signal in response to a first node being at an active potential, a second output circuit configured to transfer the clock signal at the clock signal terminal to a carry output terminal as a carry output signal in response to the first node being at the active potential, and a delay circuit configured to generate a delayed version of a carry input signal in response to the carry input signal at a carry input terminal being active, and to transfer an inactive voltage at a first voltage terminal to the signal output terminal in response to the delayed version of the carry input signal being active.

Abstract: A shift register unit, a gate driving circuit and a display device are provided. The shift register unit includes a bias control circuit. The bias control circuit is electrically connected to a pull-down node, a control clock signal terminal, and a bias voltage terminal, respectively, and is configured to control connection between the pull-down node and the bias voltage terminal under the control of a control clock signal provided by the control clock signal terminal; and the bias voltage terminal is configured to input a bias voltage signal.

Abstract: A shift register unit and a driving method thereof, a gate drive circuit, and a display device are provided. The shift register unit includes: an input circuit configured to control a potential of a first node; a first output circuit configured to output a carry signal to a first output terminal of the shift register unit through an output terminal of the first output circuit, under control of the potential and a clock signal; a second output circuit configured to output a driving signal to a second output terminal of the shift register unit, under control of the potential and the clock signal; a switching circuit configured to control the output terminal to be electrically connected to the first output terminal in response to a control signal; and a potential control circuit configured to control the output terminal to be electrically connected to a first voltage terminal.

Abstract: The present disclosure provides a shift register and a method for driving the same, a gate driving circuit, and a display apparatus. The shift register includes: a node control sub-circuit configured to control a potential at a pull-up node under control of a signal input terminal and a reset terminal; an output sub-circuit configured to provide an output signal to a signal output terminal based on a signal at a clock signal terminal under control of the pull-up node; and at least one gating sub-circuit connected to at least one de-noising node respectively, and each configured to de-noise a respective de-noising node connected thereto independently of the potential at the pull-up node under control of a trigger signal terminal, wherein the at least one de-noising node includes at least one of the pull-up node and the signal output terminal.