Abstract: Generally disclosed herein is an approach for enabling the connection of non-PCIe accelerators as PCIe devices using a Peripheral Component Interconnect Express (PCIe) abstraction layer (“PAL”). Once the operating system accesses and configures any on-SoC devices and accelerators using standard PCIe APIs, all PCIe configuration transactions may be routed to the PAL. The PAL's firmware may present the operating system with a virtual PCIe space that contains all available SoC PCIe and non-PCIe devices. The firmware of the PAL may translate PCIe configuration transactions into device-specific configuration transactions.

Abstract: Generally disclosed herein is an approach for enabling the connection of non-PCIe accelerators as PCIe devices using a Peripheral Component Interconnect Express (PCIe) abstraction layer (“PAL”). Once the operating system accesses and configures any on-SoC devices and accelerators using standard PCIe APIs, all PCIe configuration transactions may be routed to the PAL. The PAL's firmware may present the operating system with a virtual PCIe space that contains all available SoC PCIe and non-PCIe devices. The firmware of the PAL may translate PCIe configuration transactions into device-specific configuration transactions.

Abstract: Sideband signaling in Universal Serial Bus (USB) Type-C communication link allows multiple protocols that are tunneled through a USB link, where sideband signals may be provided through the sideband use (SBU) pins. Further, the SBU pins may be transitioned between different modes of sideband signals. In particular, signals in an initial mode may indicate a need or desire transition to a second mode. After a negotiation, linked devices agree to transition, the two devices may transition to the second mode. By providing this inband sideband signaling that allows mode changes, more protocols can be tunneled with accompanying sideband signaling and flexibility of the USB link is expanded.

Abstract: Sideband signaling in Universal Serial Bus (USB) Type-C communication link allows multiple protocols that are tunneled through a USB link, where sideband signals may be provided through the sideband use (SBU) pins. Further, the SBU pins may be transitioned between different modes of sideband signals. In particular, signals in an initial mode may indicate a need or desire transition to a second mode. After a negotiation, linked devices agree to transition, the two devices may transition to the second mode. By providing this inband sideband signaling that allows mode changes, more protocols can be tunneled with accompanying sideband signaling and flexibility of the USB link is expanded.

Abstract: Tunneling over Universal Serial Bus (USB) sideband channel systems and methods provide a way to tunnel I2C transactions between a master and slaves over USB 4.0 sideband channels. More particularly, a slave address table lookup (SATL) circuit is added to a host circuit. Signals from an I2C bus are received at the host, and any address associated with a destination is translated by the SATL. The translated address is passed to a low-speed interface associated with a sideband channel in the host circuit. Signals received at the low-speed interface are likewise reverse translated in the SATL and then sent out through the I2C bus. In this fashion, low-speed I2C signals may be routed over the sideband channel through the low-speed sideband interface portion of the USB interface.

Abstract: Systems and methods for time synchronization for clocks separated by a communication link allow a master clock to be positioned at a downstream-facing port or an upstream-facing port and to send synchronization commands with an associated time stamp embedded in transport layer protocol (TLP) prefixes to a slave clock. The slave clock may update its time value based on the received time stamp. Further, the slave may calculate a round trip delay between the master clock and the slave clock and use this delay calculation to correct the slave clock. The delay calculation may likewise be made using TLP prefixes. By using TLP prefixes in this fashion, the time synchronization can piggyback on existing message traffic, which reduces signaling overhead. Likewise, by using the TLP prefixes, the time synchronization may be initiated from either an upstream-facing port or a downstream-facing port.

Abstract: Systems and methods for scrambling data-port audio in SOUNDWIRE™ systems include a scramble enable feature that allows a data source to scramble an outgoing channel content with a cyclic linear feedback shift register (LFSR) using a pseudo-random binary sequence (PRBS) such as, but not limited to, the PRBS defined in the SOUNDWIRE specification. Data ports for audio sinks receiving the scrambled content descramble the content for use by the audio sink. In a specific exemplary aspect, an output of the LFSR is added or subtracted with the audio data to make the microphones independent of one another and reduce crosstalk.

Abstract: In some aspects, the present disclosure provides a method for communicating audio data. In one example, the method includes determining whether a condition for each transport opportunity on an audio channel is met based on an audio sample rate and a channel rate of the audio channel. For each transport opportunity, upon determining that the condition is met for the transport opportunity, the method also includes transmitting audio sample data over the transport opportunity or receiving audio sample data at the transport opportunity.

Abstract: Systems and methods for time synchronization for clocks separated by a communication link allow a master clock to be positioned at a downstream-facing port or an upstream-facing port and to send synchronization commands with an associated time stamp embedded in transport layer protocol (TLP) prefixes to a slave clock. The slave clock may update its time value based on the received time stamp. Further, the slave may calculate a round trip delay between the master clock and the slave clock and use this delay calculation to correct the slave clock. The delay calculation may likewise be made using TLP prefixes. By using TLP prefixes in this fashion, the time synchronization can piggyback on existing message traffic, which reduces signaling overhead. Likewise, by using the TLP prefixes, the time synchronization may be initiated from either an upstream-facing port or a downstream-facing port.

Abstract: Systems and methods for time synchronization for clocks separated by a communication link allow a master clock to be positioned at a downstream-facing port or an upstream-facing port and to send synchronization commands with an associated time stamp embedded in transport layer protocol (TLP) prefixes to a slave clock. The slave clock may update its time value based on the received time stamp. Further, the slave may calculate a round trip delay between the master clock and the slave clock and use this delay calculation to correct the slave clock. The delay calculation may likewise be made using TLP prefixes. By using TLP prefixes in this fashion, the time synchronization can piggyback on existing message traffic, which reduces signaling overhead. Likewise, by using the TLP prefixes, the time synchronization may be initiated from either an upstream-facing port or a downstream-facing port.

Abstract: Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array.

Abstract: Systems and methods for reducing latency on long distance point-to-point links where the point-to-point link is a Peripheral Component Interconnect (PCI) express (PCIE) link that modifies a receiver to advertise infinite or unlimited credits. A transmitter sends packets to the receiver. If the receiver's buffers fill, the receiver, contrary to PCIE doctrine, drops the packet and returns a negative acknowledgement (NAK) packet to the transmitter. The transmitter, on receipt of the NAK packet, resends packets beginning with the one for which the NAK packet was sent. By the time these resent packets arrive, the receiver will have had time to manage the packets in the buffers and be ready to receive the resent packets.

Abstract: Systems and methods for scrambling data-port audio in SOUNDWIRE™ systems include a scramble enable feature that allows a data source to scramble an outgoing channel content with a cyclic linear feedback shift register (LFSR) using a pseudo-random binary sequence (PRBS) such as, but not limited to, the PRBS defined in the SOUNDWIRE specification. Data ports for audio sinks receiving the scrambled content descramble the content for use by the audio sink. In a specific exemplary aspect, an output of the LFSR is added or subtracted with the audio data to make the microphones independent of one another and reduce crosstalk.

Abstract: Systems and methods for payload transport for simple pulse division multiplexed (PDM) devices provide for simple PDM devices to have a phase-locked loop (PLL) that operates at a frequency corresponding to an audio rate on an associated audio bus. Additional parameters are defined relative to a starting synchronization event. The parameters inform a simple PDM device from which bit slots to extract data or into which bit slots to write data. In a further exemplary aspect, a low-cost delay-locked loop (DLL) is used to assist the simple PDM device in calculating the designated bit slots.

Abstract: Security techniques for a Peripheral Component Interconnect (PCI) express (PCIE) system include a transport layer protocol (TLP) packet that has a prepended TLP prefix indicating the security features of the TLP packet and an integrity check value (ICV) appended to the TLP packet. The ICV is based on the TLP packet and any TLP prefixes including a security prefix. At a receiver, if the ICV does not match, then the receiver has evidence that the TLP packet may have been subjected to tampering. Further, the TLP packet may be encrypted to prevent snooping, and this feature would be indicated in the TLP prefix. Still further, the TLP prefix may include a counter that may be used to prevent replay attacks. PCIE contemplates flexible TLP prefixes, and thus, the standard readily accommodates the addition of a TLP prefix which indicates the security features of the TLP packet.

Abstract: Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array.

Abstract: Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array.

Abstract: Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array.

Abstract: Delayed bank switch commands in an audio system such as a SOUNDWIRE audio system may have slaves that have had a delay register added to register banks for each data port. When a bank switch command is received, a slave consults the delay register and delays switching by a number of frames indicated in the delay register. Such delays may be used to prevent interpreting non-audio data as part of a data stream, particularly at start up and closure of audio streams. If an audio stream is active, the delay may be set to zero. By precluding the evaluation of non-audio data, audio artifacts may be avoided and a better user experience provided.

Abstract: Updating cache devices includes a processor to detect a first set of hash functions and a first bit array corresponding to elements of a cache. In some examples, the processor detects a first instruction to add a new element to the cache and modify the first bit array based on the new element. Additionally, the processor processes a first invalidation operation and generates a second bit array and a second set of hash functions, while processing additional instructions. The processor deletes the first bit array and the first set of hash functions in response to detecting that the second bit array and the second set of hash functions have each been generated. Some examples process a second invalidation operation with the second set of hash functions and the second bit array.