Abstract: A hybrid command is proposed for interacting with a non-volatile memory device. The hybrid command enables a host connected to the non-volatile memory device to both send and receive data using a single command, which removes the need to use separate commands for sending and receiving. Using the one command rather than separate commands increases system performance.

Abstract: A hybrid command is proposed for interacting with a non-volatile memory device. The hybrid command enables a host connected to the non-volatile memory device to both send and receive data using a single command, which removes the need to use separate commands for sending and receiving. Using the one command rather than separate commands increases system performance.

Abstract: Systems and methods for decoupling host commands in a non-volatile memory system are disclosed. In one implementation, a non-volatile memory system includes a non-volatile memory and a controller in communication with the non-volatile memory. The controller is configured to translate a first command that is formatted according to a communication protocol to a second command that is formatted generically, store the first command in an expected queue, and store the second command in the expected queue with a command priority. The controller is further configured to execute the second command based on the command priority, translate a result of the executed second command into a format according to the communication protocol, and transmit the result of the executed second command in the format according to the communication protocol to a host system dependent upon a position of the first command in the expected queue.

Abstract: Systems and methods for decoupling host commands in a non-volatile memory system are disclosed. In one implementation, a non-volatile memory system includes a non-volatile memory and a controller in communication with the non-volatile memory. The controller is configured to translate a first command that is formatted according to a communication protocol to a second command that is formatted generically, store the first command in an expected queue, and store the second command in the expected queue with a command priority. The controller is further configured to execute the second command based on the command priority, translate a result of the executed second command into a format according to the communication protocol, and transmit the result of the executed second command in the format according to the communication protocol to a host system dependent upon a position of the first command in the expected queue.

Abstract: A data storage device includes a non-volatile memory and host interface circuitry. The host interface circuitry is configured, in response to receiving a first command from a host device, to access a table to determine whether to reject the first command based on an operating state of the data storage device. The data storage device also includes a processor coupled to the non-volatile memory and to the host interface circuitry. The processor is configured to program the table.

Abstract: A data storage device includes a non-volatile memory and host interface circuitry. The host interface circuitry is configured, in response to receiving a first command from a host device, to access a table to determine whether to reject the first command based on an operating state of the data storage device. The data storage device also includes a processor coupled to the non-volatile memory and to the host interface circuitry. The processor is configured to program the table.

Abstract: A digital logic simulation/emulation system (20) operates in an engaged operating mode in which a digital-logic simulation process (22) transmits stimulation-control data to a hardware pod (32) for controlling stimulation of a digital logic circuit. In response to the stimulation-control data, the hardware pod (32) performs a stimulation-response cycle, and then sends response data from the digital logic circuit to the simulation process (22). The simulation process (22) and the hardware pod (32) may also operate in a disengaged operating mode in which each operates independently of the other without exchanging stimulation-control data or response data. Operation of the system (20) in the disengaged mode commences if a disengagement event occurs in the hardware pod (32). Operation of the system (20) in the disengaged mode terminates if the simulation process (22) sends stimulation-control data to the hardware pod (32), or if the hardware pod (32) sends response data to the simulation process (22).

Abstract: A structure and a method provide data integrity for a multiprocessor system having a cache memory and a snoop tag cache. In one embodiment, the snoop tag cache copies the tags of a primary cache. Whenever a write operation occurs, the snoop tag cache is accessed to determine if the accessed tag matches a predetermined portion of the address of the memory location on which the write operation is performed. If so, a signal is sent to the CPU associated with the primary cache so that the corresponding entries in the primary cache and the snoop tag cache can be invalidated.