Abstract: A method and an apparatus for performing link equalization testing via a physical layer test and measurement system. The system includes a protocol aware test apparatus for transmitting testing data, a device under test for receiving the transmitted testing data, and an oscilloscope for receiving an output waveform from the device under test. The protocol aware test apparatus selects a first of a plurality of preset values, sends an equalization signal from the protocol aware test apparatus to the device under test, and changes a speed of communication to a predetermined speed and sends a compliance pattern to the device under test after placing the device under test in a loopback mode. A waveform output from the device under test is captured by the oscilloscope, and is analyzed to determine compliance of the device under test with a predetermined link equalization speed in accordance with a predetermined protocol.

Abstract: A method and an apparatus for testing the physical layer of high speed serial communication devices and systems with protocol awareness is disclosed. The apparatus comprises of two major blocks: a General Purpose Platform (GPP) and an Analog Front End (AFE). Physical layer testing is divided into two sets of testing procedures: Receiver and Transmitter testing. This test system can be used in a traditional BERT setting where the test system commands the Device Under Test (DUT) to be placed into either a loop back mode, or into a more advanced mode where the test system is communicating with the DUT on a protocol level and counts the frame error ratio (FER). This FER is protocol dependent and each protocol receiver has its own way of reporting transmission errors to the transmitter. The protocol awareness of this invention is capable of detecting such a level of errors.

Abstract: A method and an apparatus for testing the physical layer of high speed serial communication devices and systems with a protocol aware test and measurement system is disclosed. This system includes two major units, a General Purpose Platform (GPP) that includes a protocol awareness and is capable of traffic generation and reception at a protocol level, and an Analog Front End (AFE) that includes physical layer testing capabilities. Physical layer testing is divided into two sets of testing procedures: Receiver testing and Transmitter testing. This test system can be used in a traditional BERT setting where the test system commands the Device Under Test (DUT) to be placed into either a loop back mode and the tester is expecting the same bit flow it transmitted, coming back from the DUT, or into a more advanced mode where the test system is in communication with the DUT like a protocol exerciser and counts the frame error ratio while stressing the DUT.

Abstract: Apparatus and associated systems and methods may include one or more features for high speed transmission line structures that may substantially reduce signal degradation due to effects, such as dielectric loss, parasitic capacitance, cross-talk, and/or reflections. For example, one such feature may include a dielectric layer having a reduced thickness within at least a part of a region that extends between two conductors fabricated on a PCB (printed circuit board). In some embodiments, the dielectric layer may include a solder mask layer that is partially or substantially absent in the region between two coplanar conductors. In another embodiment, a substrate layer made of a dielectric material may include a trench in the region between the two conductors. Another such feature, for example, may include a conductor having vias spaced less than a quarter wavelength apart to substantially reduce resonance effects on propagating high frequency signals.

Abstract: Apparatus and associated systems and methods may relate to a wide bandwidth cable assembly that may include an active amplification stage to receive high frequency signals (e.g., 1 GHz or above) through a transmission line extending distally to a passive, high density signal probe stage. In an illustrative example, the probe stage may receive multiple analog or digital signals from a device under test (DUT). In some embodiments, the probe stage may include probe pins with integrated series resistance to control signal loading, and an equalizer to shape the signal path's frequency response. The amplification stage may provide a virtual ground reference for a termination impedance that may match the transmission line's impedance and may connect in series with a feedback impedance. In one example, a minimally invasive probe head may facilitate measurement of multiple channels of a high speed data bus with minimal signal distortion and/or attenuation.

Abstract: Apparatus and associated systems and methods may include one or more features for high speed transmission line structures that may substantially reduce signal degradation due to effects, such as dielectric loss, parasitic capacitance, cross-talk, and/or reflections. For example, one such feature may include a dielectric layer having a reduced thickness within at least a part of a region that extends between two conductors fabricated on a PCB (printed circuit board). In some embodiments, the dielectric layer may include a solder mask layer that is partially or substantially absent in the region between two coplanar conductors. In another embodiment, a substrate layer made of a dielectric material may include a trench in the region between the two conductors. Another such feature, for example, may include a conductor having vias spaced less than a quarter wavelength apart to substantially reduce resonance effects on propagating high frequency signals.

Abstract: Apparatus and associated systems and methods may relate to a wide bandwidth cable assembly that may include an active amplification stage to receive high frequency signals (e.g., 1 GHz or above) through a transmission line extending distally to a passive, high density signal probe stage. In an illustrative example, the probe stage may receive multiple analog or digital signals from a device under test (DUT). In some embodiments, the probe stage may include probe pins with integrated series resistance to control signal loading, and an equalizer to shape the signal path's frequency response. The amplification stage may provide a virtual ground reference for a termination impedance that may match the transmission line's impedance and may connect in series with a feedback impedance. In one example, a minimally invasive probe head may facilitate measurement of multiple channels of a high speed data bus with minimal signal distortion and/or attenuation.