Patents by Inventor Yigang ZHOU
Yigang ZHOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240338318Abstract: This application discloses a cache management method, apparatus, and system, and a storage medium, and belongs to the computer field. The system includes a processor and a memory controller. The processor and the memory controller are connected through a first channel and a second channel, the first channel is used to perform a memory read/write operation, and the second channel is used to transmit event information corresponding to the memory read/write operation. The processor is configured to send event information of a first event to the memory controller through the second channel. The memory controller is configured to manage a cache storage based on the event information, and the cache storage is configured to cache a part of data that is in the memory storage. This application can improve utilization of the cache storage.Type: ApplicationFiled: June 20, 2024Publication date: October 10, 2024Inventors: Yigang ZHOU, Xiaoming ZHU
-
Publication number: 20240338328Abstract: A data processing system includes a computing subsystem and a memory subsystem. In the computing subsystem, a processor is connected to one end of a high-speed parallel bus via a first bus interface. The processor transmits data to the memory subsystem and receives data transmitted through the high-speed parallel bus. The memory subsystem receives and transmits data to the computing subsystem through the high-speed parallel bus.Type: ApplicationFiled: June 14, 2024Publication date: October 10, 2024Inventors: Wen Yin, Wei Li, Yigang Zhou, Manbo Wu, Xianzhou Lin, Chuanwei Wen, Ruonan Wang, Yining Li
-
Publication number: 20240243559Abstract: The present disclosure discloses an isolation device for a voltage transformer cabinet including a drive shaft; a conductive ring sleeved and fixed to the drive shaft; a movable guide rod fixed to the drive shaft and the conductive ring to swing along with a rotation of the drive shaft and electrically connected with the conductive ring; a fixing post fixedly connected to the voltage transformer; a contact, installed to the fixing post through a compression spring and electrically connected with the fixing post, and keeping in electrical contact with the conductive ring under an action of the compression spring; a closing stationary contact; and a grounded stationary contact, the rotation of the drive shaft drives the movable guide rod to swing between on position in which the movable guide rod contacts the closing stationary contact and grounded position in which the movable guide rod contacts the grounded stationary contact.Type: ApplicationFiled: January 8, 2024Publication date: July 18, 2024Applicant: Schneider Electric Industries SASInventors: Min Tang, Yigang Zhou, Haifeng Lu, Yinzhong Que
-
Publication number: 20240184607Abstract: An example electronic apparatus is for accelerating a para-virtualization network interface. The electronic apparatus includes a descriptor hub performing bi-directionally communication with a guest memory accessible by a guest and with a host memory accessible by a host. The guest includes a plurality of virtual machines. The host includes a plurality of virtual function devices. The virtual machines are communicatively coupled to the electronic apparatus through a central processing unit. The communication is based upon para-virtualization packet descriptors and network interface controller virtual function-specific descriptors. The electronic apparatus also includes a device association table communicatively coupled to the descriptor hub and to store associations between the virtual machines and the virtual function devices. The electronic apparatus further includes an input-output memory map unit (IOMMU) to perform direct memory access (DMA) remapping and interrupt remapping.Type: ApplicationFiled: November 9, 2023Publication date: June 6, 2024Inventors: Yigang ZHOU, Cunming LIANG
-
Publication number: 20240154699Abstract: An optical/electrical module includes an analog equalizer and an optical/electrical conversion unit. The analog equalizer is connected to the optical/electrical conversion unit. The analog equalizer is configured to: perform first analog signal equalization processing on a first electrical signal to obtain a second electrical signal, and send the second electrical signal to the optical/electrical conversion unit, or is configured to: receive a third electrical signal from the optical/electrical conversion unit, and perform second analog signal equalization processing on the third electrical signal to obtain a fourth electrical signal. The optical/electrical conversion unit is configured to: receive the second electrical signal from the analog equalizer and convert the second electrical signal into a first optical signal. According to embodiments of this application, equalization processing may be performed on an electrical signal in an analog domain.Type: ApplicationFiled: January 18, 2024Publication date: May 9, 2024Inventors: Changzheng Su, Lei Zhao, Yigang Zhou
-
Publication number: 20240086244Abstract: A scheduling method performed by a computing device that includes a plurality of processors, a type of at least one instruction set of instruction sets supported by at least one of the plurality of processors is different from a type of an instruction set of instruction sets supported by another processor, where the scheduling method includes obtaining a type of an instruction set of an application, selecting a target processor from the plurality of processors, where the type of the instruction set of the application is a subset of types of a plurality of instruction sets of instruction sets supported by the target processor, and allocating the application to the target processor for execution.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Inventors: Yigang Zhou, Yongnian Le, Haicheng Li, Kebing Wang
-
Patent number: 11853784Abstract: An example electronic apparatus is for accelerating a para-virtualization network interface. The electronic apparatus includes a descriptor hub performing bi-directionally communication with a guest memory accessible by a guest and with a host memory accessible by a host. The guest includes a plurality of virtual machines. The host includes a plurality of virtual function devices. The virtual machines are communicatively coupled to the electronic apparatus through a central processing unit. The communication is based upon para-virtualization packet descriptors and network interface controller virtual function-specific descriptors. The electronic apparatus also includes a device association table communicatively coupled to the descriptor hub and to store associations between the virtual machines and the virtual function devices. The electronic apparatus further includes an input-output memory map unit (IOMMU) to perform direct memory access (DMA) remapping and interrupt remapping.Type: GrantFiled: December 22, 2016Date of Patent: December 26, 2023Assignee: Intel CorporationInventors: Yigang Zhou, Cunming Liang
-
Publication number: 20230409198Abstract: In a computer device, a memory sharing control device is deployed between a processor and a memory pool, and the processor accesses the memory pool via the memory sharing control device. Different processing units, such as processors or cores in processors, access one memory in the memory pool in different time periods, so that the memory is shared by a plurality of processing units, and utilization of memory resources is improved.Type: ApplicationFiled: September 4, 2023Publication date: December 21, 2023Applicant: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Yigang Zhou, Xiaoming Zhu, Guanfeng Zhou
-
Publication number: 20230198896Abstract: One example method includes receiving network topology information delivered by a topology manager, where the data center includes a plurality of servers, a plurality of electrical switches, and at least one optical cross-connect device. A data flow can be obtained. A routing policy can be configured for the data flow based on the network topology information, where the routing policy includes any one or a combination of the following routing policies: a first routing policy, where the first routing policy indicates to forward the data flow through an optical channel in the at least one optical cross-connect device; a second routing policy, where the second routing policy indicates to split the data flow into at least two sub-data flows for forwarding; or a third routing policy, where the third routing policy indicates to forward the data flow through an electrical switch of the plurality of electrical switches.Type: ApplicationFiled: February 16, 2023Publication date: June 22, 2023Inventors: Yigang ZHOU, Shengwen LU, Xiubin MAO, Zhonghua HU, Fengkai LI, Yongfeng LIU
-
Publication number: 20220404973Abstract: This application discloses a data processing method for a memory device, an apparatus, and a system, and relates to the field of data storage technologies, so that memory capacity expansion can be implemented, and the memory capacity expansion is not limited by an original quantity of DDR channels. The memory device includes a controller, a first memory, and a second memory, the controller separately communicates with a processor, the first memory, and the second memory, and read/write performance of the first memory is higher than read/write performance of the second memory. The method includes receiving an operation request of the processor, where the operation request includes a logical address, and accessing the first memory or the second memory based on the logical address.Type: ApplicationFiled: August 26, 2022Publication date: December 22, 2022Inventors: Xiaoming Zhu, Yigang Zhou
-
Patent number: 11327789Abstract: In an example, there is disclosed a computing apparatus, having: a data interface to communicatively couple to a storage pool having a plurality of disks; a virtual machine manager including a processor; and a storage coprocessor (SCP) to: create a read queue and write queue for the disks in the storage pool; receive an input/output (IO) operation from a virtual machine, the IO operation directed to a storage address located on a disk in the storage pool; and add the IO operation to the queue for the disk.Type: GrantFiled: February 17, 2017Date of Patent: May 10, 2022Assignee: Intel CorporationInventors: Gang Cao, Weihua Rosen Xu, Danny Yigang Zhou
-
Publication number: 20220124025Abstract: This application discloses a method for forwarding a packet in a data center network. A first device obtains an original packet, and adds a first source label to the original packet to obtain a first packet. The first source label includes a forwarding type, an indication field, and an interface sequence. The forwarding type indicates that the first packet supports source label forwarding, the interface sequence indicates a first source label forwarding path of the original packet, and the indication field indicates information that is about an outbound interface and that should be read from the interface sequence. The first device sends the first packet to a next-hop switch through the outbound interface corresponding to the first source label forwarding path. The next-hop switch receives the first packet, and forwards the first packet based on the first source label.Type: ApplicationFiled: December 28, 2021Publication date: April 21, 2022Applicant: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Fengkai LI, Yun QIN, Yinben XIA, Yashe LIU, Shengwei ZHENG, Shengwen LU, Yigang ZHOU
-
Publication number: 20210216453Abstract: Disclosed herein are systems and methods for isolating input/output computing resources. In some embodiments, a host device may include a processor and logic coupled with the processor, to identify a tag identifier (Tag ID) for a process or container of the host device. The Tag ID may identify a queue pair of a hardware device of the host device for an outbound transaction from the processor to the hardware device, to be conducted by the process or container. Logic may further map the Tag ID to a Process Address Space Identifier (PASID) associated with an inbound transaction from the hardware device to the processor that used the identified queue pair. The process or container may use the PASID to conduct the outbound transaction via the identified queue pair. Other embodiments may be disclosed and/or claimed.Type: ApplicationFiled: March 29, 2021Publication date: July 15, 2021Inventors: Cunming LIANG, Edwin VERPLANKE, David E. COHEN, Danny Yigang ZHOU
-
Publication number: 20200050480Abstract: In an example, there is disclosed a computing apparatus, having: a data interface to communicatively couple to a storage pool having a plurality of disks; a virtual machine manager including a processor; and a storage coprocessor (SCP) to: create a read queue and write queue for the disks in the storage pool; receive an input/output (IO) operation from a virtual machine, the IO operation directed to a storage address located on a disk in the storage pool; and add the IO operation to the queue for the disk.Type: ApplicationFiled: February 17, 2017Publication date: February 13, 2020Applicant: Intel CorporationInventors: Gang Cao, Weihua Rosen Xu, Danny Yigang Zhou
-
Publication number: 20190354387Abstract: An example electronic apparatus is for accelerating a para-virtualization network interface. The electronic apparatus includes a descriptor hub performing bi-directionally communication with a guest memory accessible by a guest and with a host memory accessible by a host. The guest includes a plurality of virtual machines. The host includes a plurality of virtual function devices. The virtual machines are communicatively coupled to the electronic apparatus through a central processing unit. The communication is based upon para-virtualization packet descriptors and network interface controller virtual function-specific descriptors. The electronic apparatus also includes a device association table communicatively coupled to the descriptor hub and to store associations between the virtual machines and the virtual function devices. The electronic apparatus further includes an input-output memory map unit (IOMMU) to perform direct memory access (DMA) remapping and interrupt remapping.Type: ApplicationFiled: December 22, 2016Publication date: November 21, 2019Inventors: Yigang ZHOU, Cunming LIANG