Abstract: Systems, methods, and techniques described here provide for a hybrid electrically erasable programmable read-only memory (EEPROM) that functions as both a single polysilicon EEPROM and a double polysilicon EEPROM. The two-in-one hybrid EEPROM can be programmed and/or erased as a single polysilicon EEPROM and/or as a double polysilicon EEPROM. The hybrid EEPROM memory cell includes a programmable capacitor disposed on a substrate. The programmable capacitor includes a floating gate forming a first polysilicon layer, an oxide-nitride-oxide (ONO) layer having disposed over a first surface of the floating gate, and a control gate forming a second polysilicon layer with the control gate formed over a first surface of the ONO layer to form a hybrid EEPROM having a single polysilicon layer and a double polysilicon EEPROM. The single polysilicon EEPROM includes the first polysilicon layer and the double polysilicon EEPROM includes the first and second polysilicon layers.

Abstract: A vertical Hall Effect element includes a low voltage P-well region disposed at a position between pickups of a vertical Hall Effect element to result in an improved sensitivity of the vertical Hall Effect element. A method results in the vertical Hall Effect element having the improved sensitivity.

Abstract: Systems, methods, and techniques described here provide for a hybrid electrically erasable programmable read-only memory (EEPROM) that functions as both a single polysilicon EEPROM and a double polysilicon EEPROM. The two-in-one hybrid EEPROM can be programmed and/or erased as a single polysilicon EEPROM and/or as a double polysilicon EEPROM. The hybrid EEPROM memory cell includes a programmable capacitor disposed on a substrate. The programmable capacitor includes a floating gate forming a first polysilicon layer, an oxide-nitride-oxide (ONO) layer having disposed over a first surface of the floating gate, and a control gate forming a second polysilicon layer with the control gate formed over a first surface of the ONO layer to form a hybrid EEPROM having a single polysilicon layer and a double polysilicon EEPROM. The single polysilicon EEPROM includes the first polysilicon layer and the double polysilicon EEPROM includes the first and second polysilicon layers.

Abstract: Systems, methods, and techniques described here provide for a hybrid electrically erasable programmable read-only memory (EEPROM) that functions as both a single polysilicon EEPROM and a double polysilicon EEPROM. The two-in-one hybrid EEPROM can be programmed and/or erased as a single polysilicon EEPROM and/or as a double polysilicon EEPROM. The hybrid EEPROM memory cell includes a programmable capacitor disposed on a substrate. The programmable capacitor includes a floating gate forming a first polysilicon layer, an oxide-nitride-oxide (ONO) layer having disposed over a first surface of the floating gate, and a control gate forming a second polysilicon layer with the control gate formed over a first surface of the ONO layer to form a hybrid EEPROM having a single polysilicon layer and a double polysilicon EEPROM. The single polysilicon EEPROM includes the first polysilicon layer and the double polysilicon EEPROM includes the first and second polysilicon layers.

Abstract: A vertical Hall Effect element includes a low voltage P-well region disposed at a position between pickups of a vertical Hall Effect element to result in an improved sensitivity of the vertical Hall Effect element. A method results in the vertical Hall Effect element having the improved sensitivity.

Abstract: A vertical Hall Effect element includes a low voltage P-well region disposed at a position between pickups of a vertical Hall Effect element to result in an improved sensitivity of the vertical Hall Effect element. A method results in the vertical Hall Effect element having the improved sensitivity.

Abstract: A fuse formed as part of an integrated circuit has cavities disposed to the sides of the fuse to provide more reliable operation with less chance of re-connection. A method of providing the fuse is also described.

Abstract: A vertical Hall Effect element includes one or more of: a low voltage P-well region disposed at a position between pickups of the vertical Hall Effect element, Light-N regions disposed under the pickups, a pre-epi implant region, or two epi regions to result in an improved sensitivity of the vertical Hall Effect element. A method results in the vertical Hall Effect element having the improved sensitivity.

Abstract: A vertical Hall Effect element includes one or more of: a low voltage P-well region disposed at a position between pickups of the vertical Hall Effect element, Light-N regions disposed under the pickups, a pre-epi implant region, or two epi regions to result in an improved sensitivity of the vertical Hall Effect element. A method results in the vertical Hall Effect element having the improved sensitivity.

Abstract: A vertical Hall Effect element includes a low voltage P-well region disposed at a position between pickups of a vertical Hall Effect element to result in an improved sensitivity of the vertical Hall Effect element. A method results in the vertical Hall Effect element having the improved sensitivity.

Abstract: A fuse formed as part of an integrated circuit has cavities disposed to the sides of the fuse to provide more reliable operation with less chance of re-connection. A method of providing the fuse is also described.

Abstract: A Hall effect element includes a Hall plate having geometric features selected to result in a highest ratio of a sensitivity divided by a plate resistance. The resulting shape is a so-called “wide-cross” shape.

Abstract: A Hall effect element includes a Hall plate having geometric features selected to result in a highest ratio of a sensitivity divided by a plate resistance. The resulting shape is a so-called “wide-cross” shape.

Abstract: A Hall effect element includes a Hall plate with an outer perimeter. The outer perimeter includes four corner regions, each tangential to two sides of a square outer boundary associated with the Hall plate, and each extending along two sides of the square outer boundary by a corner extent. The outer perimeter also includes four indented regions. Each one of the four indented regions deviates inward toward a center of the Hall plate. The Hall plate further includes a square core region centered with and smaller than the square outer boundary. A portion of each one of the four indented regions is tangential to a respective side of the square core region. Each side of the square core region has a length greater than twice the corner extent and less than a length of each side of the square outer boundary.

Abstract: A Hall effect element includes a Hall plate with an outer perimeter. The outer perimeter includes four corner regions, each tangential to two sides of a square outer boundary associated with the Hall plate, and each extending along two sides of the square outer boundary by a corner extent. The outer perimeter also includes four indented regions. Each one of the four indented regions deviates inward toward a center of the Hall plate. The Hall plate further includes a square core region centered with and smaller than the square outer boundary. A portion of each one of the four indented regions is tangential to a respective side of the square core region. Each side of the square core region has a length greater than twice the corner extent and less than a length of each side of the square outer boundary.

Abstract: Semiconductor structures are adapted to form an electrically erasable programmable read only memory (EEPROM) cell having a long retention life, and/or a reduced programming voltage, and/or a reduced semiconductor real estate, and/or a reduced number of semiconductor fabrication steps.

Abstract: Semiconductor structures are adapted to form an electrically erasable programmable read only memory (EEPROM) cell having a long retention life, and/or a reduced programming voltage, and/or a reduced semiconductor real estate, and/or a reduced number of semiconductor fabrication steps.