Patents by Inventor Yigun Ge

Yigun Ge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200092035
    Abstract: Embodiment techniques map parity bits to sub-channels based on their row weights. In one example, an embodiment technique includes allocating, from a set of sub-channels, one or more sub-channels for one or more parity bits based on row weights for sub-channels in a subset of sub-channels within the set of sub-channels, mapping information bits to remaining sub-channels in the set of sub-channels based on a reliability of the remaining sub-channels without mapping any of the information bits to the one or more sub-channels allocated for the one or more parity bits, polar encoding the information bits and the one or more parity bits based on at least the mapping of the information bits to the remaining sub-channels to obtain encoded bits, and transmitting the encoded bits to another device.
    Type: Application
    Filed: November 25, 2019
    Publication date: March 19, 2020
    Inventors: Huazi Zhang, Jiajie Tong, Rong Li, Jun Wang, Wen Tong, Yigun Ge, Xiaocheng Liu
  • Publication number: 20120137198
    Abstract: A method for decoding tail-biting convolutional codes. The method includes initializing a correction depth, selecting a first starting state from a set of encoding states, and initializing a metric value for the selected starting state as zero and the other states as infinity. The input bit stream is read and a Search Depth Viterbi algorithm (SDVA) is performed to determine path metrics and identify a minimum-metric path. The ending state for the minimum-metric path is determined and the output for this ending state is identified as “previous output.” A second starting state is set to the ending state of the minimum-metric path, and symbols equal to the correction depth from the previous output are read. The SDVA is performed on the second set of read symbols to generate a corrected output. A decoded output is generated by replacing symbols at the beginning of the previous output with the corrected output.
    Type: Application
    Filed: February 7, 2012
    Publication date: May 31, 2012
    Applicant: STMicroelectronics (Beijing) R&D Company Ltd.
    Inventors: Wuxian Shi, Juan Du, Yigun Ge, Guobin Sun