Abstract: A semiconductor device includes a substrate including at least two semiconductor chip regions and a scribe lane region disposed between the semiconductor chip regions. The semiconductor device additionally includes a first optical measurement pattern disposed on the substrate. The semiconductor device further includes a second optical measurement pattern disposed on an upper layer of the first optical measurement pattern, the second optical measurement pattern being spaced apart from the first optical measurement pattern. The semiconductor device additionally includes a three-dimensional (3D) shielding structure surrounding the first optical measurement pattern and including an electrically conductive material.

Abstract: A semiconductor device includes a substrate including at least two semiconductor chip regions and a scribe lane region disposed between the semiconductor chip regions. The semiconductor device additionally includes a first optical measurement pattern disposed on the substrate. The semiconductor device further includes a second optical measurement pattern disposed on an upper layer of the first optical measurement pattern, the second optical measurement pattern being spaced apart from the first optical measurement pattern. The semiconductor device additionally includes a three-dimensional (3D) shielding structure surrounding the first optical measurement pattern and including an electrically conductive material.

Abstract: An inductor for a system-on-a-chip and a method for manufacturing the inductor are disclosed. The inductor comprises a conductive line formed by connecting a plurality of conductive patterns grown from a seed layer formed on a lower wiring. The method comprises using an electrolytic plating process or an electroless plating process to grow the plurality of adjacent conductive patterns from the seed layer until they become connected. The method also enables adjusting the height and width of the conductive line to desired levels.

Abstract: An inductor for a system-on-a-chip and a method for manufacturing the inductor are disclosed. The inductor comprises a conductive line formed by connecting a plurality of conductive patterns grown from a seed layer formed on a lower wiring. The method comprises using an electrolytic plating process or an electroless plating process to grow the plurality of adjacent conductive patterns from the seed layer until they become connected. The method also enables adjusting the height and width of the conductive line to desired levels.

Abstract: An inductor for a system-on-a-chip and a method for manufacturing the inductor are disclosed. The inductor comprises a conductive line formed by connecting a plurality of conductive patterns grown from a seed layer formed on a lower wiring. The method comprises using an electrolytic plating process or an electroless plating process to grow the plurality of adjacent conductive patterns from the seed layer until they become connected. The method also enables adjusting the height and width of the conductive line to desired levels.