Abstract: The current invention provides a method for analyzing process variations that occur during integrated circuit fabrication. Critical dimension data is collected for each layer of the integrated circuit fabrication process for a period of time and a shift indicator that indicates variation in the critical dimension data for each layer of the integrated circuit fabrication process is calculated. A machine drift significance indicator is also calculated for each machine used in each layer of the integrated circuit fabrication process, and a maximum shift of mean value for each layer of the integrated circuit fabrication process is defined. The shift indicator, the maximum shift of mean value and the machine drift significance indicator are used to determine at least one likely cause of variation in critical dimension for each layer of the integrated circuit fabrication process.

Abstract: A method of treating the surface of a metal nitride barrier layer on an integrated circuit to reduce the movement of silicon through the barrier. The metal nitride barrier (such as TiN) is exposed to a nitrogen plasma, thereby improving the barrier properties of the metal nitride barrier.

Abstract: A method of forming an interlevel dielectric suitable for use with semiconductor integrated circuits is disclosed. The dielectric illustratively includes a triple layer sandwich of ozone-TEOS formed between two layers of plasma-enhanced TEOS. The dielectric is capable of filling high-aspect ratio trenches between runners. The ozone-TEOS is formed at a high pressure (approximately 90 Torr) to reduce hydrogen absorption. The reduced-hydrogen content ozone-TEOS is less susceptible to moisture formation and, therefore, presents less risk of degrading subsequently formed aluminum runners.

Abstract: A method for forming an ohmic contact on a GaAs semiconductor material comprising depositing a non-uniform layer of Au onto the surface layer of the semiconductor material, depositing a multi-layer ohmic contact of AuGeNi onto the non-uniform layer and alloying the ohmic contact to the semiconductor material. The non-uniform Au layer may be deposited by backscattering Au during sputter cleaning of the semiconductor surface wherein the electrode is coated with Au. After alloying, the ohmic contact comprises a two layer structure having a high density of large area NiAs(Ge) grains contacting the semiconductor material as the first layer and an AuGa phase as the top layer. The ohmic contact has reduced contact resistance and exhibits a reduction in the spread of contact resistance after high temperature annealing.