Patents by Inventor Yih-Cherng Juang

Yih-Cherng Juang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7466527
    Abstract: An electro-static discharge protection circuit including a first-LDNMOS transistor, a second-LDNMOS transistor, a first-resistor, and a gate-driven resistance is provided. The drain of the first-LDNMOS transistor is served as an electro-static input end, the P-body and source of the first-LDNMOS transistor are connected to each other. A coupling-voltage signal determines whether the first-LDNMOS transistor is turned on or not. The drain, P-body, and gate of the second-LDNMOS transistor are respectively connected to the drain of the first-LDNMOS transistor, the source of the first-LDNMOS transistor, and a common-ground potential. The first-resistor is connected between the source of the first-LDNMOS transistor and the common-ground potential.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: December 16, 2008
    Assignee: ITE Tech. Inc.
    Inventor: Yih-Cherng Juang
  • Publication number: 20040085743
    Abstract: A tape carrier package has a chip, a tape carrier and sealing material. The chip has an active surface on which a plurality of bump electrodes are centrally arranged in two rows. The tape carrier has a device hole smaller than the chip, and has a plurality of leads each of which is divided into inner lead and outer lead. The inner leads are routed inward the center of the device hole and connected to the bump electrodes, respectively. The sealing material encapsulates the active surface of the chip and the inner leads, with the outer leads being exposed.
    Type: Application
    Filed: October 27, 2003
    Publication date: May 6, 2004
    Inventor: Yih-Cherng Juang
  • Publication number: 20030043565
    Abstract: A tape carrier package has a chip, a tape carrier and sealing material. The chip has an active surface on which a plurality of bump electrodes are centrally arranged in two rows. The tape carrier has a device hole smaller than the chip, and has a plurality of leads each of which is divided into inner lead and outer lead. The inner leads are routed inward the center of the device hole and connected to the bump electrodes, respectively. The sealing material encapsulates the active surface of the chip and the inner leads, with the outer leads being exposed.
    Type: Application
    Filed: September 27, 2001
    Publication date: March 6, 2003
    Inventor: Yih-Cherng Juang