Abstract: A circuit is provided. The circuit includes a first die that includes a memory array, and the memory array includes a plurality of memory cells, a sensing element coupled to the plurality of memory cells, and a first plurality of conductive pads coupled to the sensing element. The circuit also includes a second die that includes an address decoder associated with the memory array of the first die and a second plurality of conductive pads coupled to the address decoder. The first die is coupled to the second die by an interposer. The address decoder of the second die is coupled to the sensing element of the first die. A first voltage swing of the first die is larger than a second voltage swing of the second die.

Abstract: Methods, systems, and devices for wireless communications are described. For instance, a flow control layer of a UE may provide a capability message to an application layer including an indication that the UE supports a service for providing flow control information for support of extended reality traffic and may receive a message from an application of the application layer registering a flow associated with the application with the service. The flow control layer may provide, to the application via the service, an indication that a quantity of packets or bytes in a buffer of the flow control layer fails to satisfy a threshold. The UE may obtain, from the application, a packet associated with the flow based on providing the indication that the quantity of packets or bytes in the buffer fails to satisfy the threshold and may transmit, to a network entity, a message including the obtained packet.

Abstract: An electric ratchet wrench includes a control unit, a housing unit, and a driving unit. The control unit stores a plurality of parameter sets that correspond respectively to a plurality of operating modes related respectively to different sets of a torque and a rotational speed. The housing unit includes a housing, a trigger module configured to output a trigger signal when the trigger module is operated, and an operation module configured to output a mode signal for switching between the operating modes when the operation module is operated. The control unit is configured to, in response to receipt of the mode signal, set one of the operating modes as a current operating mode, and, in response to receipt of the trigger signal, output a control signal for controlling operation of a motor according to one of the parameter sets that corresponds to the current operating mode.

Abstract: An electronic device for detecting an optical signal is provided. The electronic device for detecting the optical signal includes an optical sensor and a light-emitting element. The light-emitting element is disposed adjacent to the optical sensor. The optical sensor is configured to detect the optical signal. The light-emitting element has a first brightness during a non-detection period of the electronic device. The light-emitting element is dimmed and has a second brightness during a detection period of the electronic device. The optical sensor is configured to output a signal when the light-emitting element is dimmed. The first brightness is greater than the second brightness.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a fin-based structure formed on a substrate. The semiconductor device includes a plurality of first nanosheets, vertically spaced apart from one another, that are formed on the substrate. The semiconductor device includes a first source/drain (S/D) region electrically coupled to a first end of the fin-based structure. The semiconductor device includes a second S/D region electrically coupled to both of a second end of the fin-based structure and a first end of the plurality of first nanosheets. The semiconductor device includes a third S/D region electrically coupled to a second end of the plurality of first nanosheets. The fin-based structure has a first crystal lattice direction and the plurality of first nanosheets have a second crystal lattice direction, which is different from the first crystal lattice direction.

Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

Abstract: A sternum stabilization vest includes two chest pads and a supporting structure. Each chest pad includes: a sponge; a cloth body covering the sponge; first and second front fixing straps arranged on front side of the cloth body with the later located above the former; and first and second front adjustment rings arranged on the first and second front fixing straps, respectively. The supporting structure includes: a back supporting cloth; side fixing straps arranged on both lateral sides of the back supporting cloth; side adjustment rings arranged at the side fixing straps; and side strap bodies arranged at both lateral sides of the back supporting cloth and located below the side fixing straps. The side strap bodies are threaded through the first front adjustment rings, the side adjustment rings and the second front adjustment rings in sequence, such that the extension paths of the side strap bodies form Z-shapes.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate including an element isolation structure defining first to third active regions and first to third elements respectively in the first to third active region. The first element includes a first gate dielectric layer embedded in the first active region of the substrate and isolation structures embedded in the substrate at opposite sides of the first gate dielectric layer. Bottom surfaces of the isolation structures include first portions at the same level as a bottom surface of the element isolation structure and second portions being oblique with respective to the first portions.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, an application server may receive an indication that a handover is likely for a user equipment (UE), wherein the UE is in communication with the application server to receive a data stream. The application server may provide the data stream using values of one or more parameters to reduce an impact of a communication interruption associated with the handover. Numerous other aspects are described.

Abstract: Disclosed herein are systems, methods and apparatuses related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading.

Abstract: In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.

Abstract: A memory device includes a plurality of memory arrays, a plurality of first sense amplifiers, and a plurality of multiplexers. Each of the plurality of memory arrays includes a plurality of memory cells that are formed in a respective one of a plurality of metallization layers, which are disposed over a substrate. Each of the plurality of first sense amplifiers and a corresponding one of the memory arrays are formed in a respective one of the metallization layers. Each of the plurality of multiplexers, a corresponding one of the memory arrays, and a corresponding one of the first sense amplifiers are formed in the respective one of the metallization layers. Thus, the peripheral area of the memory device is reduced, thereby advantageously achieving higher density thereof.

Abstract: The techniques disclosed herein provide a personalized interactive timeline of user activity graphical user interface (GUI) that enables a personalized search and retrieval user experience. This is accomplished by gathering a record of user activity such as graphical captures (e.g., screenshots) of a desktop environment. A graphical capture can define a software application that is currently in focus within the desktop environment. The graphical captures are then organized into subsets based on the software application that is in focus in each of the graphical captures. The graphical captures are then further organized into sessions which are delineated by substantially continuous user interaction with the corresponding software application. A graphical segment is then generated for each session and subsequently compiled into an interactive timeline. A user can scrub through the timeline to recall previous activity.

Abstract: Systems and methods for reconfiguring application windows in a display. An example method includes displaying a first application window and a second application window; receiving a drag input for moving the first application window; based on the drag input entering an invocation region, displaying a layout menu with a plurality of display layouts, each of the display layouts including one or more snap zones; receiving a hover of the first application window over a particular snap zone of a particular display layout of the plurality of display layouts; based on the hover of the first application window over the particular snap zone, displaying a zone-indicator pane corresponding to the particular snap zone; receiving a drop input of the first application window over the particular snap zone; and in response to the drop input, resizing and repositioning the first application window according the particular snap zone.

Abstract: One aspect of this description relates to a memory array. In some embodiments, the memory array includes a first memory cell coupled between a first local select line and a first local bit line, a second memory cell coupled between a second local select line and a second local bit line, a first switch coupled to a global bit line, a second switch coupled between the first local bit line and the first switch, and a third switch coupled between the second local select line and the first switch.

Abstract: The invention provides a semiconductor layout pattern including high-voltage devices, which comprises a substrate, wherein a high-voltage device region and an MRAM (magnetic random access memory) region are adjacent to each other, wherein the MRAM region at least comprises a plurality of MRAM cells arranged in an array, wherein each MRAM cell comprises two fin structures parallel to each other and arranged along an X direction, and two gate structures parallel to each other and arranged along a Y direction. A drain metal layer is located between the two gate structures, two source metal layers are located on the other side of the two gate structures, respectively, and an MTJ (magnetic tunneling junction) element is electrically connected with the drain metal layers.

Abstract: The present application provides a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first die; a first redistribution structure positioned on the first die; a second die positioned on the first redistribution structure and comprising a first cache unit; and a third die positioned on the first redistribution structure, separated from the second die, and comprising a second cache unit. The first redistribution structure comprises: a plurality of conductive layers electrically coupled the first die and the first cache unit of the second die and electrically coupled the first die and the second cache unit of the third die, respectively and correspondingly; and a bridge layer electrically isolated from the plurality of conductive layers, electrically connected the second die and the third die. The first cache unit of the second die and the second cache unit of the third die are topographically aligned with the first die.

Abstract: A semiconductor device including a package, a lid and a thermal interface material is provided. The package includes a packaging substrate, semiconductor dies and an insulating encapsulation, wherein the semiconductor dies are disposed on and electrically connected to the packaging substrate, and the insulating encapsulation encapsulates the semiconductor dies. The lid is disposed on the packaging substrate, the lid includes a cover portion and foot portion extending from the cover portion to the packaging substrate, wherein the cover portion covers the semiconductor dies and the insulating encapsulation, the foot portion includes foot segments laterally spaced apart from one another, and the foot segments are attached to the packaging substrate. The cover portion of the lid is attached to the package through the thermal interface material.

Abstract: A method (of writing to a ferroelectric field-effect transistor (FeFET) configured as a 2-bit storage device that stores two bits, wherein the FeFET includes a first source/drain (S/D) terminal, a second S/D terminal, a gate terminal and a ferroelectric layer, a second bit being at a first end of the ferroelectric layer, the first end being proximal to the first S/D terminal) includes: setting the second bit to a logical 1 value, the setting a second bit including applying a gate voltage to the gate terminal, and applying a first source/drain voltage to the second S/D terminal; and wherein the first source/drain voltage is lower than the gate voltage.

Abstract: A memory device includes a first memory array disposed over a substrate, a second memory array disposed over the substrate and separated from the first memory array along a first direction, and a strap cell defined in the substrate and interposed between the first memory array and the second memory array. The strap cell includes a first boundary abutting the first memory array, a second boundary abutting the second memory array, a p-type well strap interposed between the first boundary and the second boundary along the first direction, and an n-type well strap spaced from the p-type well strap along the second direction. The first boundary and the second boundary extending along a second direction perpendicular to the first direction. The p-type well strap is coupled to a first power supply voltage, and the n-type well strap is coupled to a second power supply voltage.