Abstract: An architecture for connection between regions in or adjacent a semiconductor layer. According to one embodiment a semiconductor device includes a first layer of semiconductor material and a first field effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The device includes a second field effect transistor also having a first source/drain region formed in the first layer. A channel region of the second transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. A conductive layer comprising a metal is positioned between the first source/drain region of each transistor to conduct current from one first source/drain region to the other first source/drain region. In another embodiment a first device region, is formed on a semiconductor layer.

Abstract: The present invention provides a method of manufacturing a bipolar transistor. The method may comprise forming a collector in a semiconductor wafer substrate, forming a base in the collector, implanting an oxide region within said collector and over the base, and forming an emitter over the substrate such that the oxide region is located between the emitter and the base.

Abstract: An integrated electronic device includes a semiconductor substrate layer having a major surface formed along a crystal plane. In one embodiment a first conductivity type region is formed in the substrate layer and a substantially monocrystalline semiconductor layer is deposited thereon. The deposited layer includes a first portion of a second conductivity type and a second portion of the first conductivity type formed over the first portion. The first portion and the first region form a pn junction. An upper-most substrate surface formed along a first plane and a first doped region of a first conductivity type is formed above the first plane. A second doped region of a second conductivity type is formed over the first doped region resulting in formation of a p-n junction in a second plane above the first plane. Electrical connection is provided to the first doped region with a conductor formed between the first and second planes.

Abstract: The present invention provides a bipolar transistor located on a semiconductor wafer substrate. The bipolar transistor may comprise a collector located in the semiconductor wafer substrate, a base located in the collector, and an emitter located on the base and in contact with at least a portion of the base, wherein the emitter has a low K layer located therein. The low K layer may be, for example, located proximate a side of the emitter, or it may be located proximate opposing sides of the emitter. In all embodiments, however, the low K layer does not interfere with the proper functioning of the bipolar transistor, and substantially reduces the emitter-base capacitance typically associated with conventional bipolar transistors.

Abstract: The present invention provides a method of manufacturing a bipolar transistor. The method may comprise forming a collector in a semiconductor wafer substrate, forming a base in the collector, implanting an oxide region withing said collector and over the base, and forming an emitter over the substrate such that the oxide region is located between the emitter and the base.

Abstract: The present invention provides a bipolar transistor for use in increasing a speed of a flash memory cell having a source region and a drain region and first and second complementary tubs. In one embodiment, a base for the bipolar transistor is located in the first complementary tub. The first complementary tub functions as a collector for the bipolar transistor. The bipolar transistor base also uniquely functions as the source region. The bipolar transistor's emitter is also located in the first complementary tub and proximate the base. For example, the emitter may be located adjacent the base or actually located in the base. In an additional embodiment, the opposing bases and emitters are located on opposing sides of and proximate to the flash memory cell.

Abstract: An integrated circuit and a process for making the same are provided. The circuit has a nitrogen implanted emitter window, wherein the nitrogen has been implanted into the emitter window after the emitter window etch, but prior to the emitter conductor deposition. Nitrogen implantation is expected to minimize oxide growth variation.

Abstract: The present invention provides a VRG structure formed on a semiconductor wafer substrate. The VRG structure has a first source/drain region located in a semiconductor wafer substrate, and a conductive layer located adjacent the source/drain region, a second source/drain region and a conductive channel that extends from the first source/drain region to the second source/drain region. The conductive layer provides an electrical connection to the first source/drain region. The conductive layer may have a low sheet resistance that may be less than about 50 &OHgr;/square or less than about 20 &OHgr;/square, to the first source/drain region.

Abstract: A bipolar device (10) includes an oxide layer (24) which is grown on the surface (16) of a semiconductor substrate (12) by immersing the surface in ozonated deionized water. By selecting an appropriate temperature of the water and concentration of the ozone, the thickness of the film can be maintained within fine tolerances from lot to lot, and over the surface of a wafer (W) comprising the substrate.

Abstract: A device architecture and process for fabricating a semiconductor device incorporating a p-n junction. Generally, an integrated electronic device includes a substrate layer of semiconductor material having a major surface formed along a crystal plane. In a preferred embodiment, a first region of a first conductivity type is formed in the substrate layer and a substantially monocrystalline semiconductor layer is deposited on the first region. Within this layer there is a first portion of a second conductivity type and a second portion of the first conductivity type formed over the first portion. The first portion and the first surface region form a pn junction.

Abstract: An integrated circuit and a process for making the same are provided. The circuit has a nitrogen implanted emitter window, wherein the nitrogen has been implanted into the emitter window after the emitter window etch, but prior to the emitter conductor deposition. Nitrogen implantation is expected to minimize oxide growth variation.

Abstract: A BiCMOS semiconductor device and a method of forming same are disclosed. A bipolar transistor region is formed adjacent a CMOS device region within a semiconductor substrate. Carbon is implanted in an amount ranging from about 1013 to about 1014 cm−2 before forming the base, emitter and collector within the bipolar transistor region to aid in suppressing transient enhanced diffusion. The bipolar transistor region is subject to rapid thermal annealing to aid in suppressing the transient enhanced diffusion.

Abstract: A bipolar vertical PNP transistor compatible with CMOS processing and useful in a complementary BiMOS structure is characterized in that it is devoid of an epitaxial layer and employs a high-energy implanted phosphorus layer to provide N-type substrate isolation.

Abstract: The present invention provides a method of passivating a semiconductor device having a capping layer formed thereover, comprising: (1) subjecting the semiconductor device to a high pressure within a pressure chamber and (2) exposing the semiconductor device to a passivating gas. The high pressure causes the passivating gas, such as a deuterated passivating gas, to penetrate the capping layer and thereby passivate the semiconductor device. The method provided by the present invention is, therefore, particularly useful in those instances where a final passivation step is desired after the formation of the capping layer. It is believed that the hydrogen isotope bonds to dangling bond sites within the semiconductor device, which are most often present at a silicon/silicon dioxide interface. Further, because of their larger mass, these hydrogen isotope atoms are not easily removed by electron flow during the operation of the device as is the case with the lighter hydrogen atoms.

Abstract: A bipolar fabrication process, illustratively suited for integration into a conventional CMOS process to thereby form a BiCMOS integrated circuits is disclosed. The collector and base are formed through multiple implants and a single masking step to thereby provide a continuous low resistance collector region.