Abstract: A semiconductor structure is provided. A second conductivity type well region is formed on a first conductivity type substrate. A second conductivity type diffused source and second conductivity type diffused drain are formed on the first conductivity type substrate. A gate structure is formed on the second conductivity type well region between the second conductivity type diffused source and the second conductivity type diffused drain. First conductivity type buried rings are arranged in a horizontal direction, and formed in the second conductivity type well region, and divide the second conductivity type well region into an upper drift region and a lower drift region.

Abstract: A semiconductor structure is provided. A second conductivity type well region is disposed on a first conductivity type substrate. A gate structure comprising a first sidewall and second sidewall is provided. The first sidewall is disposed on the second conductivity type well region. A second conductivity type diffused source is disposed on the first conductivity type substrate outside of the second sidewall. A second conductivity type diffused drain is disposed on the second conductivity type well region outside of the first sidewall. First conductivity type buried rings are arranged in a horizontal direction, separated from each other, and formed in the second conductivity type well region. Doped profiles of the first conductivity type buried rings gradually become smaller in a direction from the second conductivity type diffused source to the second conductivity type diffused drain.

Abstract: Lateral diffused metal oxide semiconductor (LDMOS) devices with electrostatic discharge (ESD) protection capability are presented for integrated circuits. The LDMOS device includes a semiconductor substrate with an epi-layer thereon. Patterned isolations are disposed on the epi-layer, thereby defining a first active region and a second active region. An N-type double diffused drain (NDDD) region is formed in the first active region and a N+ doped drain region is disposed in the NDDD region. A P-body diffused region is formed in the second active region, wherein the NDDD region and the P-body diffused region are separated with a predetermined distance exposing the epi-layer. An N+ doped source region and a P+ diffused region are disposed in the P-body diffused region. A gate structure is disposed between the N+ doped source region and the N+ doped drain region. An additional heavily doped region is formed between the semiconductor and the epi-layer.

Abstract: A semiconductor structure is provided. A second conductivity type well region is formed on a first conductivity type substrate. A second conductivity type diffused source and second conductivity type diffused drain are formed on the first conductivity type substrate. A gate structure is formed on the second conductivity type well region between the second conductivity type diffused source and the second conductivity type diffused drain. First conductivity type buried rings are arranged in a horizontal direction, and formed in the second conductivity type well region, and divide the second conductivity type well region into an upper drift region and a lower drift region.

Abstract: A semiconductor structure is provided. A second conductivity type well region is disposed on a first conductivity type substrate. A gate structure comprising a first sidewall and second sidewall is provided. The first sidewall is disposed on the second conductivity type well region. A second conductivity type diffused source is disposed on the first conductivity type substrate outside of the second sidewall. A second conductivity type diffused drain is disposed on the second conductivity type well region outside of the first sidewall. First conductivity type buried rings are arranged in a horizontal direction, separated from each other, and formed in the second conductivity type well region. Doped profiles of the first conductivity type buried rings gradually become smaller in a direction from the second conductivity type diffused source to the second conductivity type diffused drain.

Abstract: Lateral diffused metal oxide semiconductor (LDMOS) devices with electrostatic discharge (ESD) protection capability are presented for integrated circuits. The LDMOS device includes a semiconductor substrate with an epi-layer thereon. Patterned isolations are disposed on the epi-layer, thereby defining a first active region and a second active region. An N-type double diffused drain (NDDD) region is formed in the first active region and a N+ doped drain region is disposed in the NDDD region. A P-body diffused region is formed in the second active region, wherein the NDDD region and the P-body diffused region are separated with a predetermined distance exposing the epi-layer. An N+ doped source region and a P+ diffused region are disposed in the P-body diffused region. A gate structure is disposed between the N+ doped source region and the N+ doped drain region. An additional heavily doped region is formed between the semiconductor and the epi-layer.

Abstract: A method for forming a dielectric layer with a low dielectric constant (low-k) is described. A semiconductor substrate is provided. A dielectric layer is formed on the substrate. A doping step is performed on the dielectric layer. An annealing step is performed and a gas is simultaneously fed so that the dielectric layer is converted into the low-k dielectric layer.

Abstract: A method of protecting gate oxide. A chip having a gate thereon is provided. The gate structure comprises a gate oxide layer and a gate electrode. The gate is covered by a dielectric layer. A protection layer is formed on the dielectric layer. The protection layer is pattern to remain a part of the protection layer aligned over the gate.

Abstract: A method for measuring a capacitance of a passive device region. The passive device region is formed on a substrate having a conductive type different from that of the passive device region. Two bias voltages are applied to two terminals of the passive device region. By measuring the distance between these two terminals and the width of the passive device region, plus the grading coefficients of both area effect and sidewall effect, capacitance induced at both terminals can be derived.

Abstract: A method of manufacturing an electrostatic discharge protective circuit. A substrate having an inner circuit region and an electrostatic discharge protective circuit is provided. The inner circuit region comprises a first gate electrode, a source/drain region and a first suicide layer formed on the first gate electrode. The electrostatic discharge protective circuit region comprises a second gate electrode and a second silicide layer formed on the second gate electrode. A salicide block layer is formed to cover the electrostatic discharge protective circuit region. A salicide process is performed. The salicide block layer is removed to expose the electrostatic discharge protective circuit region.

Abstract: A method of fabricating a semiconductor device for preventing an antenna effect. In the invention, there is no additional mask layer or specific process performed. Thus, the fabrication cost does not increase. In addition, extra electrons are released through a path formed in the invention during the plasma-etching step. An antenna effect thus does not occur. The reliability of the semiconductor device is increased.

Abstract: A method for manufacturing an electrostatic discharge (ESD) protective circuit. By using the method according to the invention, since the Zener diode, which has low trigger voltage and low power consumption, is formed in the electrostatic protective circuit, the protective ability of the ESD protective circuit is greatly improved as the integration is relatively high. Furthermore, it is necessary to use an extra photo mask as the ESD implantation step and the Zener breakdown implantation step are performed when the internal circuit and the ESD protective circuit are formed simultaneously, so that the cost is reduced.

Abstract: A method for avoiding plasma damage. In a semiconductor substrate of a first conductive type, a second conductive type well is formed. While forming the second conductive well, a high-energy dopant is doped into the semiconductor substrate. The high energy makes a depletion region between the substrate and the well have defects. A leakage path is thus formed. The leakage path can direct any charged carriers coming from plasma to avoid accumulation of the charged carriers in the well. Thus, the electrical characteristics of the well or even the quality of gate oxide formed thereon is prevented from being degraded.

Abstract: An improved method for fabricating an ESD protection device so as to avoid ESD damage to a wafer. The improved method includes simultaneously forming an internal circuit and the ESD protection device without additional photomask or other process. The improved method uses a P.sup.+ doped region to take the place of an N.sup.- doped region of an interchangeable source/drain region with a LDD structure for the ESD protection device, of which its trigger voltage is adjusted by simply varying the P.sup.+ concentration.

Abstract: The present invention is a method of manufacturing porous-Si capacitors for use in semiconductor memories. The present invention uses a silicon oxide layer as an etching mask to etch a polysilicon layer to form a porous-Si structure. The etching process is performed to etch a portion of the polysilicon layer and to etch away the remaining HSG-Si. Next, an oxide layer which is in micro grooves is removed to define a porous-Si bottom storage. The present invention can be used to increase the surface area of the capacitor.

Abstract: A CMOS device with buried contacts is formed using a polysilicon stack layer and twin-well and liquid phase deposition (LPD) processes. A gate oxide layer and a first polysilicon layer are formed on a substrate. Then the gate oxide and first polysilicon layer are etched to form gate structures. A polysilicon stack layer is formed on the gate structures. The polysilicon stack layer and the first polysilicon layer are anisotropically dry etched, forming first trenches that expose portions of the gate oxide and portions of the substrate defining S/D regions for a NMOSFET. A NMOS lightly doped drain (LDD) with halo doping profile is implanted. A first LPD oxide is selectively formed in the first trenches. Subsequently, a first heavy ion implantation is performed into the polysilicon stack layer for forming the source, drain, gate and buried contacts of the NMOSFET. Trenches are formed in the polysilicon stack layer and first polysilicon layer to define S/D regions and buried contacts for a PMOSFET.

Abstract: A self-aligning process for adding a barrier metal to the source and drain regions of metal oxide semiconductors is presented. An oxide sidewall spacer is first formed on the sides of upwardly protruding gate regions. A barrier metal is then added to the entire surface, followed by adding a layer of resist material. The resist material is added in layers with each layer spun until the top surface is nearly smooth. An anisotropical etch is done to remove the resist everywhere except over the source and drain regions, which regions are depressed due to the upwardly protruding gate region and a surrounding upwardly protruding insulating material. The exposed barrier metal is etched away and the remaining resist is stripped, leaving a layer of barrier metal only over the source and drain regions.