Abstract: A non-volatile memory cell includes a floating gate transistor having a floating gate. A method for operating the non-volatile memory cell includes, during a program operation, performing an initial program searching operation to identify a first initial value of a threshold voltage of the floating gate transistor, coupling the floating gate of the floating gate transistor to a first program voltage to raise the threshold voltage of the floating gate transistor, performing a program searching operation to identify a first variation of the threshold voltage, generating a second program voltage according to the first variation of the threshold voltage, and coupling the floating gate of the floating gate transistor to the second program voltage to raise the threshold voltage of the floating gate transistor.

Abstract: A non-volatile memory cell includes a floating gate transistor having a floating gate. A method for operating the non-volatile memory cell includes, during a program operation, performing an initial program searching operation to identify a first initial value of a threshold voltage of the floating gate transistor, coupling the floating gate of the floating gate transistor to a first program voltage to raise the threshold voltage of the floating gate transistor, performing a program searching operation to identify a first variation of the threshold voltage, generating a second program voltage according to the first variation of the threshold voltage, and coupling the floating gate of the floating gate transistor to the second program voltage to raise the threshold voltage of the floating gate transistor.

Abstract: A non-volatile memory cell includes a floating gate transistor having a floating gate. A method for operating the non-volatile memory cell includes, during a program operation, performing an initial program searching operation to identify a first initial value of a threshold voltage of the floating gate transistor, coupling the floating gate of the floating gate transistor to a first program voltage to raise the threshold voltage of the floating gate transistor, performing a program searching operation to identify a first variation of the threshold voltage, generating a second program voltage according to the first variation of the threshold voltage, and coupling the floating gate of the floating gate transistor to the second program voltage to raise the threshold voltage of the floating gate transistor.

Abstract: A non-volatile memory cell includes a floating gate transistor having a floating gate. A method for operating the non-volatile memory cell includes, during a program operation, performing an initial program searching operation to identify a first initial value of a threshold voltage of the floating gate transistor, coupling the floating gate of the floating gate transistor to a first program voltage to raise the threshold voltage of the floating gate transistor, performing a program searching operation to identify a first variation of the threshold voltage, generating a second program voltage according to the first variation of the threshold voltage, and coupling the floating gate of the floating gate transistor to the second program voltage to raise the threshold voltage of the floating gate transistor.

Abstract: A control voltage searching method is provided. Firstly, a control pulse with a preset control voltage and a preset pulse width is generated, and a control action on a memory cell. If the pulse count of the control pulse is smaller than a first number, the control voltage plus a first increment is set as an updated value of the control voltage. If the pulse count of the control pulse is not smaller than a first number, a first-stage verifying action is performed to judge whether the memory cell passes a first-stage verification test. If the memory cell passes the first-stage verification test, a second-stage verifying action is performed to judge whether the memory cell passes a second-stage verification test. If the memory cell passes the second-stage verification test, a target value of the control voltage is acquired.

Abstract: A control voltage searching method is provided. Firstly, a control pulse with a preset control voltage and a preset pulse width is generated, and a control action on a memory cell. If the pulse count of the control pulse is smaller than a first number, the control voltage plus a first increment is set as an updated value of the control voltage. If the pulse count of the control pulse is not smaller than a first number, a first-stage verifying action is performed to judge whether the memory cell passes a first-stage verification test. If the memory cell passes the first-stage verification test, a second-stage verifying action is performed to judge whether the memory cell passes a second-stage verification test. If the memory cell passes the second-stage verification test, a target value of the control voltage is acquired.

Abstract: A memory device, a peripheral circuit thereof and a single-byte data write method thereof are provided. The peripheral circuit includes a Y decoder, a page buffer, and a write circuit. The write circuit is coupled to a memory array and the page buffer through the Y decoder and receives a byte of program data. The write circuit is based on a memory address corresponding to the program data to receive a plurality of bytes of array data stored in the memory array through the Y decoder, and the read array data is written to page buffer through the Y decoder. Next, the program data is written to the memory array through the write circuit and Y decoder, and the array data is written to the memory array by the page buffer.

Abstract: A memory device, a peripheral circuit thereof and a single-byte data write method thereof are provided. The peripheral circuit includes a Y decoder, a page buffer, and a write circuit. The write circuit is coupled to a memory array and the page buffer through the Y decoder and receives a byte of program data. The write circuit is based on a memory address corresponding to the program data to receive a plurality of bytes of array data stored in the memory array through the Y decoder, and the read array data is written to page buffer through the Y decoder. Next, the program data is written to the memory array through the write circuit and Y decoder, and the array data is written to the memory array by the page buffer.

Abstract: A non-volatile memory apparatus and a data verification method thereof are provided. The non-volatile memory apparatus includes a plurality of memory cells, a page buffer, a write circuit, a sense amplifier, and a sense and compare circuit. The page buffer stores a plurality of buffered data and programs the plurality of memory cells according to the plurality of buffered data. The write circuit receives a program data or a rewrite-in data and writes the program data or the rewrite-in data to the page buffer. The sense amplifier senses data read from the memory cells for generating a read-out data. The sense and compare circuit reads the buffered data, and compares the read-out data and a compared buffered data to generate a rewrite-in data. The sense and compare circuit determines the rewrite-in data to be the buffered data or an inhibiting data according to the compared result.

Abstract: A non-volatile memory apparatus and a data verification method thereof are provided. The non-volatile memory apparatus includes a plurality of memory cells, a page buffer, a write circuit, a sense amplifier, and a sense and compare circuit. The page buffer stores a plurality of buffered data and programs the plurality of memory cells according to the plurality of buffered data. The write circuit receives a program data or a rewrite-in data and writes the program data or the rewrite-in data to the page buffer. The sense amplifier senses data read from the memory cells for generating a read-out data. The sense and compare circuit reads the buffered data, and compares the read-out data and a compared buffered data to generate a rewrite-in data. The sense and compare circuit determines the rewrite-in data to be the buffered data or an inhibiting data according to the compared result.

Abstract: An output current of a memory cell is sensed by a sensing circuit for distinguishing a program state and an erase state of the memory cell. The sensing circuit includes a reference transistor, a P-type MOSFET, and an N-type MOSFET. The P-type MOSFET has a gate connected to a memory cell for receiving an output current of the memory cell. The N-type MOSFET has a drain connected to a drain of the first P-type MOSFET, and has a source connected to ground. The inverter has an input terminal connected to the drain of the first N-type MOSFET. The voltage at an output terminal of the inverter is used for indicating the program state or the erase state of the memory cell. The reference transistor has a gate connected to a reference signal, and has a drain connected to the gate of the P-type MOSFET.

Abstract: An output current of a memory cell is sensed by a sensing circuit for distinguishing a program state and an erase state of the memory cell. The sensing circuit includes a reference transistor, a P-type MOSFET, and an N-type MOSFET. The P-type MOSFET has a gate connected to a memory cell for receiving an output current of the memory cell. The N-type MOSFET has a drain connected to a drain of the first P-type MOSFET, and has a source connected to ground. The inverter has an input terminal connected to the drain of the first N-type MOSFET. The voltage at an output terminal of the inverter is used for indicating the program state or the erase state of the memory cell. The reference transistor has a gate connected to a reference signal, and has a drain connected to the gate of the P-type MOSFET.