Abstract: A liquid crystal display device and a display flickering method are provided. The display flickering method includes receiving a first instruction signal and a color selection signal from a time sequence control circuit; outputting a data signal and a control signal according to the first instruction signal and the color selection signal; displaying an image by at least one frame display frequency according to the data signal; providing a backlight source for illuminating the display panel by at least one backlight flicker frequency according to the control signal, in which the display panel displays the at least one image having at least one frame flicker frequency according to the at least one backlight flicker frequency and the at least one frame display frequency.

Abstract: A liquid crystal display device and a display flickering method are provided. The display flickering method includes receiving a first instruction signal and a color selection signal from a time sequence control circuit; outputting a data signal and a control signal according to the first instruction signal and the color selection signal; displaying an image by at least one frame display frequency according to the data signal; providing a backlight source for illuminating the display panel by at least one backlight flicker frequency according to the control signal, in which the display panel displays the at least one image having at least one frame flicker frequency according to the at least one backlight flicker frequency and the at least one frame display frequency.

Abstract: A single clock driven shift register comprising multiple stages is provided. The (M)th stage comprises a latch unit, a logic unit, and a non-overlap buffer. The latch unit latches an input signal from the (M?1)th stage according to a clock signal. The logic unit connecting to an output terminal of the latch unit deals with an output signal of the latch unit and the clock signal with an NAND logic calculation. The non-overlap buffer connecting to the output terminal of the logic unit comprises at least three inverters connected in a serial, and an output signal of the first inverter coupled to the output terminal of the logic unit is input to an latch unit of the (M+1)th stage. Meanwhile, an output signal of the non-overlap buffer of the (M?1)th stage is input to the non-overlap buffer or the logic unit to delay the output signal of the non-overlap buffer.